AD7148 datasheet(32/56 Pages) AD

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AD7148

Rev. 0 | Page 32 of 56

POWER-UP SEQUENCE

When the AD7148 is powered up, the following sequence is

recommended when initially developing the AD7148 and host

microprocessor serial interface:

Turn on the power supplies to the AD7148.

Write to the Bank 2 registers at Address 0x080 through

Address 0x0BF. These registers are contiguous, so a

sequential register write sequence can be applied.

Note that the Bank 2 register values are unique for each

application. Register values come from characterization

of the sensor in the application and may be provided by

Analog Devices after the sensor board has been developed.

Write to the Bank 1 registers at Address 0x000 through

Address 0x007, as outlined in the following list.

Caution

At this time, Address 0x001 must remain set to Default

Value 0x0000 during this contiguous write operation.

Address 0x000 = 0x0B2

Address 0x001 = 0x000

Address 0x002 = 0x3230 (depends on number of

conversion stages used)

Address 0x003 = 0x0419

Address 0x004 = 0x0832

Address 0x005 = interrupt enable register; depends

on required interrupt behavior

Address 0x006 = interrupt enable register; depends

on required interrupt behavior

Address 0x007 = interrupt enable register; depends

on required interrupt behavior

Write to the Bank 1 register, Address 0x001 = 0x00FF;

depends on number of conversion stages used.

Read back the corresponding interrupt status register

at Address 0x008, Address 0x009, or Address 0x00A.

The address to be read back is determined by the

interrupt output configuration, as explained in the

Interrupt Output section.

Note that the specific registers required to be read back

depend on each application. For buttons, the interrupt

status registers are read back, while other sensors read

data back according to the requirements of the slider or

wheel algorithm. Analog Devices provides this informa-

tion after the sensor board has been developed.

Repeat Step 5 every time INT is asserted.

FIRST CONVERSION SEQUENCE

CONVERSION

STAGE

AD7148

INTERRUPT

POWER

SUPPLY

HOST

SERIAL

INTERFACE

CONVERSION STAGES DISABLED

10 11

910 110

SECOND CONVERSION

SEQUENCE

THIRD CONVERSION

SEQUENCE

Figure 44. Recommended Start-Up Sequence

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