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AD7148

Rev. 0 | Page 28 of 56

I2C-COMPATIBLE SERIAL INTERFACE

The AD7148 supports the industry standard 2-wire I2C serial inter-

face protocol. The two wires associated with the I2C timing are the

SCLK and the SDA inputs. The SDA is an I/O pin that allows both

always a slave device on the I2C serial interface bus.

It has a single fixed 7-bit device address, Address 0101 110. The

AD7148 responds when the master device sends its device address

over the bus. The AD7148 cannot initiate data transfers on the bus.

Table 15. AD7148 I2C Device Address

DEV

Data Transfer

Data is transferred over the I2C serial interface in 8-bit bytes.

The master initiates a data transfer by establishing a start condition,

defined as a high-to-low transition on the serial data line, SDA,

while the serial clock line, SCLK, remains high. This indicates

that an address/data stream follows.

All slave peripherals connected to the serial bus respond to the

start condition and shift in the next eight bits, consisting of a

7-bit address (MSB first) plus an R/W bit that determines the

direction of the data transfer. The peripheral whose address

corresponds to the transmitted address responds by pulling the

data line low during the ninth clock pulse. This is known as the

acknowledge bit. All other devices on the bus now remain idle

while the selected device waits for data to be read from, or written

to it. If the R/W bit is a 0, the master writes to the slave device.

If the R/W bit is a 1, the master reads from the slave device.

Data is sent over the serial bus in a sequence of nine clock pulses:

eight bits of data followed by an acknowledge bit from the slave

device. Transitions on the data line must occur during the low

period of the clock signal and remain stable during the high

period because a low-to-high transition when the clock is high

can be interpreted as a stop signal. The number of data bytes

transmitted over the serial bus in a single read or write operation

is limited only by what the master and slave devices can handle.

When all data bytes are read or written, a stop condition is estab-

lished. A stop condition is defined by a low-to-high transition

on SDA, while SCLK remains high. If the AD7148 encounters

a stop condition, it returns to its idle condition, and the address

pointer register resets to Address 0x00.

Writing Data over the I2C Bus

The process for writing to the AD7148 over the I2C bus is shown in

Figure 38 and Figure 40. The device address is sent over the bus

followed by the R/W bit set to 0. This is followed by two bytes of

data that contain the 10-bit address of the internal data register

to be written. The following bit map shows the upper register

address bytes. Note that Bit 7 to Bit 2 in the upper address byte

are don’t care bits. The address is contained in the 10 LSBs of

the register address bytes.

MSB

LSB

Address

Bit 9

Address

Bit 8

The following bit map shows the lower register address bytes.

MSB

LSB

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Reg

Add

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

The third data byte contains the eight MSBs of the data to be

written to the internal register. The fourth data byte contains

the eight LSBs of data to be written to the internal register.

The AD7148 address pointer register automatically increments

after each write, allowing the master to sequentially write to all

registers on the AD7148-1 in the same write transaction. However,

the address pointer register does not wrap around after the last

address.

Any data written to the AD7148 after the address pointer has

reached its maximum value is discarded.

All registers on the AD7148 have 16 bits. Two consecutive 8-bit

data bytes are combined and written to the 16-bit registers. To

avoid errors, all writes to the device must contain an even number

of data bytes.

To finish the transaction, the master generates a stop condition

on SDO or generates a repeat start condition if the master is to

maintain control of the bus.

Reading Data over the I2C Bus

To read from the AD7148, the address pointer register must first

be set to the address of the required internal register. The master

performs a write transaction and writes to the AD7148 to set the

address pointer. The master then outputs a repeat start condition

to keep control of the bus or, if this is not possible, ends the write

transaction with a stop condition. A read transaction is initiated,

with the R/W bit set to 1.

The AD7148 supplies the upper eight bits of data from the

addressed register in the first readback byte, followed by the

lower eight bits in the next byte. This operation is shown in

Figure 39 and Figure 40.

Because the address pointer automatically increases after each

read, the AD7148 continues to output readback data until the

master puts a no acknowledge and a stop condition on the bus.

If the address pointer reaches its maximum value, and the master

continues to read from the part, the AD7148 repeatedly sends

data from the last register addressed.

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