AD7148 datasheet(3/56 Pages) AD

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AD7148

Rev. 0 | Page 3 of 56

SPECIFICATIONS

VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CAPACITANCE-TO-DIGITAL CONVERTER

Update Rate

24.25

25.75

8 conversion stages in sequencer;

decimation rate = 256

Resolution

Bits

CINx Input Range

±8

No Missing Codes

Bits

Guaranteed by design, not production tested

Total Unadjusted Error

±20

Output Noise (Peak-to-Peak)

Codes

Decimation rate = 128

Codes

Decimation rate = 256

Output Noise (RMS)

0.8

Codes

Decimation rate = 128

0.5

Codes

Decimation rate = 256

CSTRAY Offset Range

±20

6-bit DAC

CSTRAY Offset Resolution

0.32

Low Power Mode Delay Accuracy

% of 200 ms, 400 ms, 600 ms, or 800 ms

EXCITATION SOURCE

Frequency

250

kHz

Output Voltage

VCC

Oscillating

ACSHIELD

Short-Circuit Source Current

Short-Circuit Sink Current

Maximum Output Load

150

Capacitance load on ACSHIELD to ground

LOGIC INPUTS (SCLK, SDA,)

Input High Voltage, VIH

0.7 × VDRIVE

Input Low Voltage, VIL

0.4

Input High Voltage, IIH

−1

μA

VIN = VDRIVE

Input Low Voltage, IIL

μA

VIN = GND

Hysteresis

150

OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)

Output Low Voltage, VOL

0.4

ISINK = −1 mA

Output High Leakage Current, IOH

+0.1

±1

μA

VOUT = VDRIVE

POWER

VCC

2.6

3.3

3.6

VDRIVE

1.65

3.6

Serial interface operating voltage

ICC

0.9

In full power mode, VCC + VDRIVE

15.5

21.5

μA

Low power mode, converter idle, VCC + VDRIVE

2.3

7.5

μA

Full shutdown, VCC + VDRIVE

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