P

S

P

SCL

SDA

VIH

VIL

VIH

VIL

A

Bit7(MSB)

Bit6

Bit0(LSB)

tw(SCLL)

tw(SCLH)

tr

tf

tsu(START)

th(START)

tsu(SDA)

th(SDA)

t(BUS)

tr

tf

tsu(STOP)

1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

Sr

Rd

A

8

1

1

1

1

ByteCountN

A

A

A

P

DataByte0

…

DataByteN-1

8

CommandCode

7

Slave Address

8

8

1

7

1

1

1

1

S

Slave Address

Wr

A

A

A

8

1

1

1

1

DataByte0

A

A

A

P

8

DataByteN-1

…

8

DataByte1

8

CommandCode

ByteCount=N

8

1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

S

Rd

A

8

1

1

DataByte

A

P

CommandCode

8

7

Slave Address

1

7

1

1

8

1

1

1

S

Slave Address

Wr

A

A

A

P

DataByte

CommandCode

8

16

CDCE937-Q1, CDCEL937-Q1

SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: CDCE937-Q1 CDCEL937-Q1

Submit Documentation Feedback

Copyright © 2010–2016, Texas Instruments Incorporated

10.5.4 Byte Write Programming Sequence

Figure 8. Byte Write Protocol

10.5.5 Byte Read Programming Sequence

Figure 9. Byte Read Protocol

10.5.6 Block Write Programming Sequence

(1)

Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose

and must not be overwritten.

Figure 10. Block Write Protocol

10.5.7 Block Read Programming Sequence

Figure 11. Block Read Protocol

10.5.8 Timing Diagram for the SDA and SCL Serial Control Interface

Figure 12. Timing Diagram for SDA and SCL Serial Control Interface