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CDCE937 Datasheet(PDF) 12 Page - Texas Instruments |
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CDCE937 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 39 page ![]() EEPROM Xin/CLK Xout VDD GND Input Clock Vctr Vddout VCXO XO LVCMOS Y1 Y2 LV CMOS Pdiv1 10-Bit Y3 Y4 Y5 Y6 LV CMOS Pdiv7 Pdiv6 LV CMOS LV CMOS Pdiv5 Pdiv4 LV CMOS LV CMOS Pdiv3 Pdiv2 7-Bit LV CMOS Programming and SDA/SCL Register Y7 PLL Bypass PLL1 with SSC PLL Bypass PLL 2 with SSC PLL Bypass PLL 3 with SSC S0 S1/SDA S2/SCL 7-Bit 7-Bit 7-Bit 7-Bit 7-Bit Copyright © 2016, Texas Instruments Incorporated 12 CDCE937-Q1, CDCEL937-Q1 SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: CDCE937-Q1 CDCEL937-Q1 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated 10.2 Functional Block Diagram 10.3 Feature Description 10.3.1 Control Terminal Setting The CDCEx937-Q1 has three user-definable control terminals (S0, S1, and S2) that allow external control of device settings. They can be programmed to any of the following setting: • Spread spectrum clocking selection → spread type and spread amount selection • Frequency selection → switching between any of two user-defined frequencies • Output state selection → output configuration and power down control The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings. Table 1. Control Terminal Definition EXTERNAL CONTROL BITS PLL1 SETTING PLL2 SETTING PLL3 SETTING Y1 SETTING Control Function PLL Frequency Selection SSC Selection Output Y2/Y3 Selection PLL Frequency Selection SSC Selection Output Y4/Y5 Selection PLL Frequency Selection SSC Selection Output Y6/Y7 Selection Output Y1 and Power-Down Selection |
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