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CDCE937 Datasheet(PDF) 11 Page - Texas Instruments |
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CDCE937 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 39 page ![]() 11 CDCE937-Q1, CDCEL937-Q1 www.ti.com SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016 Product Folder Links: CDCE937-Q1 CDCEL937-Q1 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated 10 Detailed Description 10.1 Overview The CDCE937-Q1 and CDCEL937-Q1 devices are modular PLL-based low-cost high-performance programmable clock synthesizers, multipliers, and dividers. It generates up to seven output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to three independent configurable PLLs. The CDCEx937-Q1 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL937-Q1 and from 2.5 V to 3.3 V for CDCE937-Q1. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal (that is, PWM signal). The deep M/N divider ratio allows the generation of zero ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as 27 MHz. All PLLs supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is a common technique to reduce electro-magnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL. The device supports non-volatile EEPROM programming for ease-customized application. It is preset to a factory default configuration (see Default Device Setting). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through SDA and SCL bus, a 2-wire serial interface. Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for output-disable function. The CDCEx937-Q1 operates in 1.8-V environment. It is characterized for operation from –40°C to 125°C. |
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