CDCE937 datasheet(8/39 Pages) TI2

8 / 39 page

CDCE937-Q1, CDCEL937-Q1

SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: CDCE937-Q1 CDCEL937-Q1

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Electrical Characteristics (continued)

over recommended operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

VIL

SDA and SCL input low voltage(6)

0.3 × VDD

VOL

SDA low-level output voltage

IOL = 3 mA, VDD = 1.7 V

0.2 × VDD

SCL/SDA Input capacitance

VI = 0 V or VDD

EEPROM

EEcyc

Programming cycles of EEPROM

1000

cycles

EEret

Data retention

years

8.6 Timing Requirements

over recommended ranges of supply voltage, load, and operating ambient temperature (see Figure 12)

MIN

NOM

MAX

UNIT

CLK_IN

fCLK

LVCMOS clock input frequency

PLL bypass mode

160

MHz

PLL mode

160

tr / tf

Rise and fall time CLK signal (20% to 80%)

dutyCLK

Duty cycle CLK at VDD/2

40%

60%

SDA and SCL

fSCL

SCL clock frequency

Standard mode

100

kHz

Fast mode

400

tsu(START)

START setup time (SCL high before SDA low)

Standard mode

4.7

µs

Fast mode

0.6

th(START)

START hold time (SCL low after SDA low)

Standard mode

µs

Fast mode

0.6

tw(SCLL)

SCL low-pulse duration

Standard mode

4.7

µs

Fast mode

1.3

tw(SCLH)

SCL high-pulse duration

Standard mode

µs

Fast mode

0.6

th(SDA)

SDA hold time (SDA valid after SCL low)

Standard mode

3.45

µs

Fast mode

0.9

tsu(SDA)

SDA setup time

Standard mode

250

Fast mode

100

SCL/SDA input rise time

Standard mode

1000

Fast mode

300

SCL/SDA input fall time, standard mode and fast mode

300

tsu(STOP)

STOP setup time

Standard mode

µs

Fast mode

0.6

tBUS

Bus free time between a STOP and START condition

Standard mode

4.7

µs

Fast mode

1.3

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