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CDCE937-Q1, CDCEL937-Q1

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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016

Product Folder Links: CDCE937-Q1 CDCEL937-Q1

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Copyright © 2010–2016, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions.

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage, VDD

–0.5

2.5

V

Input voltage, VI

(2) (3)

–0.5

VDD + 0.5

V

Output voltage, VO

(2)

–0.5

Vddout + 0.5

V

Input current, II (VI < 0 and VI > VDD)

20

mA

Continuous output current, IO

50

mA

Storage temperature, Tstg

–65

150

°C

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

8.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1)

±2000

V

Charged-device model (CDM),

per AEC Q100-011

All pins

±500

Corner pins

±750

(1)

For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family

(SCAA085).

(2)

Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ± 120 ppm

applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VDD

Device supply voltage

1.7

1.8

1.9

V

VO

Output Yx supply voltage, Vddout

CDCE937-Q1

2.3

3.6

V

CDCEL937-Q1

1.7

1.9

VIL

Low-level input voltage LVCMOS

0.3 × VDD

V

VIH

High-level input voltage LVCMOS

0.7 × VDD

V

VI(thresh) Input voltage threshold LVCMOS

0.5 × VDD

V

VIS

Input voltage

S0

0

1.9

V

S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD

0

3.6

VI(CLK)

Input voltage range CLK

0

1.9

V

IOH /IOL

Output current

Vddout = 3.3 V

±12

mA

Vddout = 2.5 V

±10

Vddout = 1.8 V

±8

CL

Output load LVCMOS

10

pF

TA

Ambient temperature

–40

125

°C

CRYSTAL/VCXO(1)

fXtal

Crystal input frequency (fundamental mode)

8

27

32

MHz

ESR

Effective series resistance

100

Ω

fPR

Pulling range (0 V

≤ Vctrl ≤ 1.8 V)(2)

±120

±150

ppm

Vctrl

Frequency control voltage

0

VDD

V

C0/C1

Pullability ratio

220

CL

On-chip load capacitance at Xin and Xout

0

20

pF