6

CDCE937-Q1, CDCEL937-Q1

SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: CDCE937-Q1 CDCEL937-Q1

Submit Documentation Feedback

Copyright © 2010–2016, Texas Instruments Incorporated

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)

(1)

THERMAL METRIC(2)

CDCE937-Q1, CDCEL937-Q1

UNIT

PW (TSSOP)

20 PINS

RθJA

Junction-to-ambient thermal resistance

Airflow = 0 lfm

89

°C/W

Airflow = 150 lfm

75

Airflow = 200 lfm

74

Airflow = 250 lfm

74

Airflow = 500 lfm

69

RθJC(top)

Junction-to-case (top) thermal resistance

31

°C/W

RθJB

Junction-to-board thermal resistance

55

°C/W

ψJT

Junction-to-top characterization parameter

0.8

°C/W

ψJB

Junction-to-board characterization parameter

49

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

—

°C/W

(1)

All typical values are at respective nominal VDD.

8.5 Electrical Characteristics

over recommended operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

IDD

Supply current (see Figure 1)

All outputs off, f(CLK) = 27 MHz,

f(VCO) = 135 MHz

All PLLS on

29

mA

Per PLL

9

IDDOUT

Output supply current (see Figure 2)

No load, all outputs on,

fOUT = 27 MHz

CDCE937,

VDDOUT = 3.3 V

3.1

mA

CDCEL937,

VDDOUT = 1.8 V

1.5

IDD(PD)

Power-down current

Every circuit powered down except SDA and SCL,

fIN = 0 MHz, VDD = 1.9 V

50

µA

V(PUC)

Supply voltage Vdd threshold for power-up

control circuit

0.85

1.45

V

f(VCO)

VCO frequency range of PLL

80

230

MHz

fOUT

LVCMOS output frequency

Vddout = 3.3 V

230

MHz

Vddout = 1.8 V

230

LVCMOS PARAMETER

VIK

LVCMOS input voltage

VDD = 1.7 V, II = –18 mA

–1.2

V

II

LVCMOS input current

VI = 0 V or VDD, VDD = 1.9 V

±5

µA

IIH

LVCMOS input current for S0/S1/S2

VI = VDD, VDD = 1.9 V

5

µA

IIL

LVCMOS input current for S0/S1/S2

VI = 0 V, VDD = 1.9 V

–6

µA

CI

Input capacitance at Xin/Clk

VI(Clk) = 0 V or VDD

6

pF

Input capacitance at Xout

VI(Xout) = 0 V or VDD

2

Input capacitance at S0/S1/S2

VIS = 0 V or VDD

3

LVCMOS PARAMETER, Vddout = 3.3 V (CDCE937)

VOH

LVCMOS high-level output voltage

Vddout = 3 V, IOH = –0.1 mA

2.9

V

Vddout = 3 V, IOH = –8 mA

2.4

Vddout = 3 V, IOH = –12 mA

2.2

VOL

LVCMOS low-level output voltage

Vddout = 3 V, IOL = 0.1 mA

0.1

V

Vddout = 3 V, IOL = 8 mA

0.5

Vddout = 3 V, IOL = 12 mA

0.8

tPLH,

tPHL

Propagation delay

All PLL bypass

3.2

ns

tr/tf

Rise and fall time

Vddout= 3.3 V (20%–80%)

0.6

ns