INA2227 datasheet(21/43 Pages) TI2

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Table 7-4. CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11-8

ACC_RST

R/W

0000b

Writing a one to these bits resets the energy registers and clears any

overflow flags.

Bit11 = reserved.

Bit10 = reserved.

Bit9 = Channel 2 energy reset, overflow clear.

Bit8 = Channel 1 energy reset, overflow clear.

Power up default: 0000b = All channels active

Bits are reset back to 0 after write.

CNVR_MASK

R/W

Setting this bit high configures the ALERT pin to be asserted when

conversions are complete.

0b = Disable conversion ready flag on ALERT pin

1b = Enables conversion ready flag on ALERT pin

ALERT remains asserted until the CVRF field in the flags register is

read.

ENOF_MASK

R/W

When set to 1, the Alert pin toggles when an energy overflow condition

occurs on any of the enabled channels

ALERT_LATCH

R/W

When set to 1 the state of the Alert pin latches during fault conditions. To

clear the alert the alert flags register must be read and the fault condition

removed.

ALERT_POL

R/W

When this bit is set to 1, the alert pin toggles from low to high during a

fault condition. When set to 0 (default), the alert pin toggles from high to

low during faults.

3-0

RANGE

R/W

0000b

Enables the selection of the shunt full scale input range for each

channel.

Bit3 = reserved.

Bit2 = reserved.

Bit1 = Channel 2 range selection.

Bit0 = Channel 1 range selection.

range selection bit = 0 selects ±81.92mV

range selection bit = 1 selects ±20.48mV

0000b = all channels set to ±81.92mV range

Return to the Summary Table.

7.1.3 CALIBRATION Registers

The calibration registers shown in Table 7-5 must be programmed to receive valid current, power, and energy

results after initial power up, power cycle events, or on device enable.

Table 7-5. INA2227 Calibration Registers

Address

0x05

CALIBRATION_CH1

R/W

0x0D

CALIBRATION_CH2

R/W

This register provides the device with the value of the shunt resistor that are present to create the measured

differential voltage. This register also sets the resolution of the Current Register. Programming this register sets

the Current_LSB and the Power_LSB.

Table 7-6. Calibration Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

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INA2227

SBOSAL5 – JUNE 2025

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