AFE5804 datasheet(37/82 Pages) TI2

37 / 82 page

ADS5294

www.ti.com

SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

Product Folder Links: ADS5294

Submit Documentation Feedback

Table 4. PLL Configuration When Decimation by 4 is Used

ADC Fs

FUNCTION

≤ 48

Disable PLL auto state switch and put

PLL in state 1

0xD1

0x0040

≤ Fs ≤ 80

Disable PLL auto state switch and put

PLL in state 2

0xD1

0x00C0

≥ 72

Disable PLL auto state switch and put

PLL in state 3

0xD1

0x0140

Table 5. PLL Configuration When Decimation by 8 is Used

ADC Fs

FUNCTION

≤ 80

Disable PLL auto state switch and put

PLL in state 1

0xD1

0x0040

≤ Fs ≤ 80

Disable PLL auto state switch and put

PLL in state 2

0xD1

0x00C0

9.4 Device Functional Modes

ADC Output Resolution and LVDS Serialization Rate Modes: The LVDS serialization rate can be programmed as

10, 12, 14, or 16 bits by the EN_BIT_SER register bit.

Output Data Rate Modes: The density of output data payload can be set to 1X or 2X mode by using the EN_SDR

can be distributed by one pair LVDS data lane or two pairs of LVDS data lanes. Please see the description of

Registers 0x50 to 0x55 in the Programmable Mapping Between Input Channels and Output Pins section. When

the decimation feature is used, the LVDS output rate can be reduced to 1/2, 1/4, and 1/8 of ADC sampling rate

as Output Data Rate Control shows. The flexible output data rate modes give users a wide selection of different

speed FPGAs.

Power Modes: The device can be configured via SPI or pin settings to a complete power-down mode and via pin

settings to a partial power-down (standby mode). During these two modes (complete and partial power-down),

different internal functions stay powered up, resulting in different power consumption and wake-up times. In the

partial power-down mode, all LVDS data lanes are powered down. The bit clock and frame clock lanes remain

enabled to save time to sync again on the receiver side. However, in the complete power-down mode all lanes

are powered down and thus this mode requires more time to wake-up because the bit clock and frame clock

lanes must sync again with the receiver device.

LVDS Test Pattern Mode: The ADC data coming out of the LVDS outputs can be replaced by different kinds of

test patterns. Note that the test patterns replace the data streaming out of the ADCs. The different test patterns

are described in LVDS Test Patterns.

9.5 Programming

9.5.1 Serial Interface

ADS5294 has a set of internal registers that can be accessed by the serial interface formed by pins CSZ (Serial

interface Enable – Active Low), SCLK (Serial Interface Clock), and SDATA (Serial Interface Data).

When CSZ is low,

•

Serial shift of bits into the device is enabled

•

Serial data (SDATA) is latched at every rising edge of SCLK

•

SDATA is loaded into the register at every 24th SCLK rising edge.

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CSZ pulse. The first eight bits form the register address and the remaining 16

bits form the register data. The interface works with SCLK frequencies from 15 MHz down to very low speeds (a

few Hertz) and also with non-50% SCLK duty cycle.

AFE5804 Datasheet(PDF) 37 Page - Texas Instruments

AFE5804 Datasheet(HTML) 37 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL