AFE5804 datasheet(57/82 Pages) TI2

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EN_SDR = 1, FALL_SDR = 0

ADCLKp

LCLKp

OUTp

ADCLKp

LCLKp

OUTp

EN_SDR = 1, FALL_SDR = 1

ADS5294

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SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

Product Folder Links: ADS5294

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In addition to programming the phase of the LCLK in the DDR mode, the device also operates in SDR mode by

setting bit EN_SDR to 1. In SDR mode, the bit clock (LCLK) is output at 14-times the input clock, or twice the

rate as in DDR mode. Depending on the state of FALL_SDR, the LCLK may be output in either of the two

manners shown in Figure 59. As can be seen in Figure 59, only the LCLK rising (or falling edge) is used to

capture the output data in SDR mode. The SDR mode does not work well beyond 40 MSPS because the LCLK

frequency will become very high.

Figure 59. SDR Interface Modes

9.6.1.12 Output Data Rate Control

Table 20. Output Data Rate Control

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

DATA_RATE<1> DATA_RATE<0>

In the default mode of operation, the data rate at the output of the ADS5294 is at the sampling rate of the ADC

which is true even when the custom pattern generator is enabled. In addition, both output data rate and sampling

rate can be configured to a sub-multiple of the input clock rate.

With the DATA_RATE<1:0> control, the output data rate is programmed to be a sub-multiple of the ADC

sampling rate. This feature is used to lower the output data rate, for example, when the decimation filter is used.

Without enabling the decimation filter, the sub-multiple ADC sampling rate feature is used.

The different settings are listed in Table 21.

Table 21. Output Data Rates

DATA_RATE<1>

DATA_RATE<0>

OUTPUT DATA RATE

Same as ADC sampling rate

1 / 2 of ADC sampling rate

1 / 4 of ADC sampling rate

AFE5804 Datasheet(PDF) 57 Page - Texas Instruments

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