DAC38RF80IAAV datasheet(40/160 Pages) TI2

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Table 7-6. Receiver Equalization Configuration

EFFECT

[1-0]

No equalization. The equalizer provides a flat response at the maximum gain. This setting may

be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than

frequency dependent loss.

Fully adaptive equalization. The zero position is determined by the selected operating rate, and the

low frequency gain of the equalizer is determined algorithmically by analyzing the data patterns and

transition positions in the received data. This setting should be used for most applications.

Precursor equalization analysis. The data patterns and transition positions in the received data

are analyzed to determine whether the transmit link partner is applying more or less precursor

equalization than necessary.

Postcursor equalization analysis. The data patterns and transition positions in the received data

are analyzed to determine whether the transmit link partner is applying more or less post-cursor

equalization than necessary.

[2]

Default

Boost. Equalizer gain boosted by 6 dB, with a 20% reduction in bandwidth, and an increase of

5mW power consumption. May improve performance over long links.

Table 7-7. Receiver Equalizer Hold

EQHOLD

EFFECT

Equalizer adaption enabled. The equalizer adaption and analysis algorithm is enabled. This should be the default

state.

Equalizer adaption held. The equalizer is held in its current state. Additionally, the adaption and analysis algorithm is

reset.

Table 7-8. Relationship Between Lane Rate and SerDes PLL Output Frequency

EQBOOST

GAIN BOOST (dB)

BANDWIDTH CHANGE (%)

POWER INCREASE (mW)

-30

-20

When EQ is set to 010 or 011, the equalizer is reconfigured to provide analytical data about the amount of pre

and post cursor equalization respectively present in the received signal. This can in turn be used to adjust the

equalization settings of the transmitting link partner, where a suitable mechanism for communicating this data

back to the transmitter exists. Status information is provided by setting field DTEST in register DTEST (8.5.76) to

“0111” for EQOVER and “0110” for EQUNDER. The procedure is as follows:

1. Enable the equalizer by setting fields EQHLD low and EQ to “001” (register SRDS_CFG1 8.5.86). Allow

sufficient time for the equalizer to adapt;

2. Set EQHLD to 1 to lock the equalizer and reset the adaption algorithm. This also causes both EQOVER and

EQUNDER to become low;

3. Wait at least 48 UI, and proportionately longer if the CDR activity is less than 100%, to make sure the 1 on

EQHLD is sampled and acted upon;

4. Set EQ to “010” or “011”, and EQHLD to 0. The equalization characteristics of the received signal are

analyzed (the equalizer response will continue to be locked);

5. Wait at least 150 × 103 UI to allow time for the analysis to occur, proportionately longer if the CDR activity is

less than 100%;

6. Examine EQOVER and EQUNDER for results of analysis

• If EQOVER is high, it indicates the signal is over equalized;

• If EQUNDER is high, it indicates the signal is under equalized;

7. Set EQHLD to 1;

8. Repeat items 3–7 if required;

9. Set EQ to “001”, and EQHLD to 0 to exit analysis mode and return to normal adaptive equalization.

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

www.ti.com

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