DAC38RF80IAAV datasheet(59/160 Pages) TI2

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7.3.16 Multiband DUC (multi-DUC)

Each DAC output in the DAC38RFxx is supported by a dual band digital upconverter (DUC), which is called a

multi-DUC.Figure 7-13 shows the signal processing features of each of the two multi-DUCs. The two paths are

identical and independent. The SPI interface registers for the multi-DUCs are addressed through paging, with

page 0 supporting multi-DUC1 and page 1 supporting multi-DUC2. Register PAGE_SET (7.5.8) is used to set

the pages. Both pages can be selected at the same time to program both multi-DUCs simultaneously with the

same settings.

Each multi-DUC has 2 DUC channels, called path AB and path CD. The output of one multi-DUC can be added

to the signal of the other multi-DUC to allow a configuration with 4 total DUCs summed together for 1 DAC.

After quadrature modulation is a sin(x)/x compensation filter, followed by the multiband summation block. The

multi-band summation block had the ability to add the signals from the other multi-DUC for a combined 4 DUCs,

each with independent frequency control. The final block is an output delay block with 0 – 15 sample range.

sin(x)

48-bit

NCO2

cos

sin

48-bit

NCO1

cos

sin

CMIX control

(±n*Fs/4)

Input

Mux

Multiband

summation

sin(x)

PAP

Gain

PAP

Gain

From 2nd

multi-DUC

Delay

Path AB

Path CD

Figure 7-13. DAC38RFxx multi-DUC Signal Processing Block Diagram

7.3.16.1 Multi-DUC input

Each multi-DUC, accepts data from up to 8 SerDes lanes. A crossbar switch allows any SerDes lane to be

mapped to any other SerDes lane. The crossbar switch is controlled by fields OCTETPATHx_SEL (x = [0..7]) in

Registers JESD_CROSSBAR1 (7.5.57) and JESD_CROSSBAR2 (7.5.58).

As shown in Table 7-9, the multiband DUC can be configured as either a single DUC with 1 IQ input, or a dual

DUC with 2 IQ inputs, which is selected by asserting field DUAL_IQ in register MULTIDUC_CFG1 (7.5.13).

7.3.16.2 Interpolation Filters

The digital upconverter first increases the sample rate of the IQ signal from the input sample rate to the final

DAC sample rate through a series of interpolation filters. Different sets of filters are used to achieve different

rates, as shown in Table 7-34. The interpolation rate is selected by field INTERP in register MULTIDUC_CFG1

(7.5.13).

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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DAC38RF80IAAV Datasheet(PDF) 59 Page - Texas Instruments

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