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DAC38RF80IAAV Datasheet(PDF) 79 Page - Texas Instruments

Part # DAC38RF80IAAV
Description  DAC38RFxx Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  160 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF80IAAV Datasheet(HTML) 79 Page - Texas Instruments

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Table 7-43. Register Summary (continued)
Address
Reset
Acronym
Register Name
Section
0x69
0x0000
JESD_ALM_L5
JESD Alarms for Lane 5
7.5.64
0x6A
0x0000
JESD_ALM_L6
JESD Alarms for Lane 6
7.5.65
0x6B
0x0000
JESD_ALM_L7
JESD Alarms for Lane 7
7.5.66
0x6C
0x0000
ALM_SYSREF_PAP
SYSREF and PAP Alarms
7.5.67
0x6D
0x0000
ALM_CLKDIV1
Clock Divider Alarms 1
7.5.68
0x6E-0x77
0x0000
Reserved
Reserved
Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1)
0x0A
0xFC03
CLK_CONFIG
Clock Configuration
7.5.69
0x0B
0x0022
SLEEP_CONFIG
Sleep Configuration
7.5.70
0x0C
0xA002
CLK_OUT
Divided Output Clock Configuration
7.5.71
0x0D
0xF000
DACFS
DAC Fullscale Current
7.5.72
0x0E-0x0F
0x0000
Reserved
Reserved
0x10
0x0000
LCMGEN
Internal sysref generator
7.5.73
0x11
0x0000
LCMGEN_DIV
Counter for internal sysref generator
7.5.74
0x12
0x0000
LCMGEN_SPISYSREF
SPI SYSREF for internal sysref generator
7.5.75
0x13-0x1A
0x0000
Reserved
Reserved
0x1B
0x0000
DTEST
Digital Test Signals
7.5.76
0x1C-0x22
0x0000
Reserved
Reserved
0x23
0xFFFF
SLEEP_CNTL
Sleep Pin Control
7.5.77
0x24
0x1000
SYSR_CAPTURE
SYSREF Capture Circuit Control
7.5.78
0x25-0x30
0x0000
Reserved
Reserved
0x31
0x0200
CLK_PLL_CFG
Clock Input and PLL Configuration
7.5.79
0x32
0x0308
PLL_CONFIG1
PLL Configuration 1
7.5.80
0x33
0x4018
PLL_CONFIG2
PLL Configuration 2
7.5.81
0x34
0x0000
LVDS_CONFIG
LVDS Output Configuration
7.5.82
0x35
0x0018
PLL_FDIV
Fuse farm clock divider
7.5.83
0x36-0x3A
0x0000
Reserved
Reserved
0x3B
0x1802
SRDS_CLK_CFG
Serdes Clock Configuration
7.5.84
0x3C
0x8228
SRDS_PLL_CFG
Serdes PLL Configuration
7.5.85
0x3D
0x0088
SRDS_CFG1
Serdes Configuration 1
7.5.86
0x3E
0x0909
SRDS_CFG2
Serdes Configuration 2
7.5.87
0x3F
0x0000
SRDS_POL
Serdes Polarity Control
7.5.88
0x40-0x75
0x0000
Reserved
Reserved
0x76
0x0000
SYNCBOUT
JESD204B SYNCB Output
7.5.89
(1)
Reflect immediately on system condition and error condition.
www.ti.com
DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93



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