DAC38RF80IAAV datasheet(52/160 Pages) TI2

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7.3.12 SerDes Test Modes through IEEE 1500 Programming

DAC38RFxx also provide a number of advanced diagnostic capabilities controlled by the IEEE 1500 interface.

These are:

• Accumulation of pattern verification errors;

• The ability to map out the width and height of the receive eye, known as Eye Scan;

• Rreal-time monitoring of internal voltages and currents;

The SerDes blocks support the following IEEE1500 instructions:

Table 7-24. IEEE1500 Instruction for SerDes Receivers

INSTRUCTION

OPCODE

DESCRIPTION

ws_bypass

0x00

Bypass. Selects a 1-bit bypass data register. Use when accessing other macros on the same

IEEE1500 scan chain.

ws_cfg

0x35

Configuration. Write protection options for other instructions.

ws_core

0x30

Core. Fields also accessible through dedicated core-side ports.

ws_tuning

0x31

Tuning. Fields for fine tuning macro performance.

ws_debug

0x32

Debug. Fields for advanced control, manufacturing test, silicon characterization and debug.

ws_unshadowed

0x34

Unshadowed. Fields for silicon characterization.

ws_char

0x33

Char. Fields used for eye scan.

The data for each SerDes instruction is formed by chaining together sub-components called head, body

(receiver or transmitter) and tail. DAC38RFxx uses two SerDes receiver blocks R0 and R1, each of which

contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head, receive

lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for each

instruction is given as follows:

Note

All multi-bit signals in each chain are packed with bits reversed for example, mpy[7:0] in ws_core

head subchain is packed as {retime, enpll, mpy[0:7], vrange, lb[0:1]}. All DATA REGISTER READS

from SerDes Block R0 should read 1 bit more than the desired number of bits and discard the first bit

received on TDO for example,, to read 40-bit data from R0 block, 41 bits should be read off from TDO

and the first bit received should be discarded. Similarly, any data written to SerDes Block R0 Data

Registers should be prefixed with an extra 0.

Table 7-25. ws_cfg Chain

FIELD

DESCRIPTION

HEAD (STARTING FROM THE MSB OF CHAIN)

RETIME

No function.

CORE_WE

Core chain write enable.

RECEIVER (FOR EACH LANE 0, 1, 2, 3)

CORE_WE

Core chain write enable.

TUNING_WE

Tuning chain write enable.

DEBUG_WE

Reserved.

CHAR_WE

Char chain write enable.

UNSHADOWED_WE

Reserved.

TAIL (ENDING WITH THE LSB OF CHAIN)

CORE_WE

Core chain write enable.

TUNING_WE

Tuning chain write enable.

DEBUG_WE

Reserved.

RETIME

No function.

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

www.ti.com

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