Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

DAC38RF80IAAV Datasheet(PDF) 80 Page - Texas Instruments

Part # DAC38RF80IAAV
Description  DAC38RFxx Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  160 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF80IAAV Datasheet(HTML) 80 Page - Texas Instruments

Back Button DAC38RF80IAAV Datasheet HTML 76Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 77Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 78Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 79Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 80Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 81Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 82Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 83Page - Texas Instruments DAC38RF80IAAV Datasheet HTML 84Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 80 / 160 page
background image
7.5.1 Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
Figure 7-34. Chip Reset and Configuration Register (RESET_CONFIG)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-44. RESET_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15
SPI_RESET
RW
0
This will reset all the SPI registers once programmed.
14
ALM_OUT_POL
RW
1
Changes the polarity of the alarm output.
0= active low
1= active high
13
ALM_OUT_ENA
RW
0
Turn on the alarm pin
12
SYSCLK_ENA
RW
1
Turns on the dividers for the SYSCLK to the Fusefarm
11
AUTOLOAD_TRIG
RW
1
Causes a Fuse AUTOLOAD to be executed.
10:7
Reserved
RW
0000
Reserved
6
ONE_DAC_ONLY
RW
0
When set high only the SLICE0 is available.
5
ONE_LINK_ONLY
RW
0
This needs to be set high when a single link setup is being
programmed to get the correct TXENABLE signal generation
4:2
Reserved
RW
000
Reserved
1
INIT_SLICE1
RW
1
Puts the multi-DAC2 JESD into initialization state
0
INIT_SLICE0
RW
1
Puts the multi-DAC1 JESD into initialization state
DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023
www.ti.com
80
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com