DAC38RF80IAAV datasheet(41/160 Pages) TI2

41 / 160 page

Note

When changing EQ from one non-zero value to another, EQHLD must already be 1. If this is not

the case, there is a chance the equalizer could be reset by a transitory input state (that is, if EQ is

momentarily 000). EQHLD can be set to 0 at the same time as EQ is changed.

As the equalizer adaption algorithm is designed to equalize the post cursor, EQOVER or EQUNDER

will only be set during post cursor analysis if the amount of post cursor equalization required is more

or less than the adaptive equalizer can provide.

7.3.5 JESD204B Descrambler

The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x14 + x15. From

the JESD204B specification, the scrambling/descrambling process only occurs on the user data, not on the code

group synchronization or the ILA sequence. Each multi-DUC has a separate descrambler that can be enabled

independently. The descrambler is enabled by field SCR in the multi-DUC paged register JESD_N_HD_SCR

(8.5.49).

7.3.6 JESD204B Frame Assembly

The DAC38RFxx may be programmed as a single or dual DAC device, with one JESD RX block designated for

each DAC. The two JESD RX blocks can be programmed to operate as two separate links or as a single link.

The JESD204B defines the following parameters:

• L is the number of lanes

• M is the number of I or Q streams per device (2 = 1 IQ pair, 4 = 2 IQ pairs, 8 = 4 IQ pairs)

• F is the number of octets per frame clock period

• S is the number of samples per frame

• HD is the High-Density bit which controls whether a sample may be divided over more lanes

• N = NPRIME is the number of bits per sample (12 or 16 - bits)

Fields K and L are found in multi-DUC paged register JESD_K_L (8.5.46), M and S in multi-DUC paged register

JESD_M_S (8.5.48), and N, NPRIME and HD in multi-DUC paged register JESD_N_HD_SCR (8.5.49).

Table 7-9 lists the available JESD204B formats, interpolation rates and sample rate limits for the DAC38RFxx.

The ranges are limited by the SerDes PLL VCO frequency range, the SerDes PLL reference clock range, the

maximum SerDes line rate, and the maximum DAC sample frequency. Table 7-10 through Table 7-22 lists the

frame formats for each mode. In the frame format tables, i CH (N) [x:y] and q CH (N) [x:y] are bits x through y of

the I and Q samples at time N of DUC channel CH. If [x..y] is not listed, the full sample is assumed. For example,

i0(0)[15:8] are bits 15 – 8 of the I sample at time 0 of DUC #0, and q1(1) is the full Q sample at time 1 of DUC

#1.

Table 7-9. JESD204B Formats for DAC38RFxx

L-M-F-S-Hd

1 TX

L-M-F-S-Hd

2 TX

Frame

Format

Input

Resolution

IQ Pairs Per

DAC

Interp

Input Rate

Max (MSPS)

fDAC Max

(MSPS)

DAC38RF83,

DAC38RF80

DAC38RF93,

DAC38RF90

DAC38RF85,

DAC38RF84

(1 TX only)

82121

1 TX: Table

7-10

1250

7500

√

1125

9000

√

750

9000

√

562.5

9000

√

42111

84111

1 TX: Table

7-11

2 TX: Table

7-12

1250

7500

√

1125

9000

√

900

9000

√

750

9000

√

562.5

9000

√

500

9000

√

375

9000

√

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SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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