DAC38RF80IAAV datasheet(67/160 Pages) TI2

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Normal

Attenuate

Wait

Gain

pap_trig=1

wait_cnt_load_r=1

wait_cnt_load_r=0

pap_trig=0

pap_gain=1

pap_trig=1

Figure 7-24. PAP Gain State Machine

The normal operating condition for the PAP block is the NORMAL state in Figure 7-24. However, when the

PAP block detects an error condition it sets the pap_trig signal to ‘1’ causing a state transition from NORMAL

operation to the ATTENUATE state.

In the ATTENUTATE state the data path gain is scaled from 1.0 down to 0.0 by a programmable step amount

set by fields PAPAB_GAIN_STEP in register PAP_GAIN_AB (7.5.31) and PAPCD_GAIN_STEP in register

PAP_GAIN_CD (7.5.33). This value is always positive with the decimal place located between the MSB and

MSB-1. Unity is equal to “1000000000”. Each clock cycle (16 samples) the PAP_GAIN is stepped down by

PAPAB_GAIN_STEP and PAPCD_GAIN_STEP until the gain is 0.

After PAP_GAIN is 0, the state machine moves on to the WAIT state. Here a programmable counter counts clock

cycles to allow the condition for the pap_trig to be fixed. Fields PAPAB_WAIT in register PAP_WAIT_AB (7.5.32)

and PAPCD_WAIT in register PAP_WAIT_CD (7.5.34) are used to select the number of clock cycles (samples

= 16 x PAPAB_WAIT or 16 x PAPCD_WAIT) to wait before moving to the next state. Once the WAIT counter

equals zero and pap_trig=’0’, the state machine moves on to the GAIN state. If the WAIT equals 0 but pap_trig

still equals ‘1’ then the state machine stays in the WAIT state until pap_trig =’0’.

7.3.18 Gain Block

The GAIN block also has additional output gain control through fields GAINAB in register GAINAB (7.5.39) and

GAINCD in register GAINCD (7.5.40). Similar to PAP_GAIN value, the output gain is always positive with unity

when GAINAB or GAINCD = ”010000000000”.

To reduce the power, the gain block clock has been gated whenever the pap is disabled and GAINAB or

GAINCD is set to unity.

7.3.19 Output Summation

The OUTSUM block allows addition of samples from each DUC in the multi-DUC. It is also possible to add the

output samples from the adjacent multi-DUC. Field OUTSUM_SEL in register OUTSUM (7.5.22) controls the

summation for each multi-DUC. The functionality of the block can be represented by the following equation:

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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DAC38RF80IAAV Datasheet(PDF) 67 Page - Texas Instruments