DAC38RF80IAAV datasheet(77/160 Pages) TI2

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at once, rather than in pieces after each individual register write. For a field that spans multiple registers, all

non-AUTOSYNC registers for the field must be written first before the actual AUTOSYNC register.

2. No RESET Value: These are NORMAL registers, but the reset value cannot be specified. This could be

because the register has some read_only bits or some internal logic partially controls the bit values.

3. READ_ONLY (R): Registers that can only be read.

7.4.5.2 WRITE_TO_CLEAR (W0C)

These registers are just like NORMAL registers with one exception. They can be written and read, however,

when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is

written to ‘0’. This way interrupts will be captured and stay constant until cleared by the user.

7.4.5.3 Writing to Reserved Bits

Registers with reserved bits must have these bits written as described in the register map when writing to this

register is required, “1” must be written to this bit. If the reserved bit is a “0”, a “0” would have to be written to this

location.

7.5 Register Maps

Table 7-43. Register Summary

Address

Reset

Acronym

Section

General Configuration Registers (PAGE_SET[2:0] = 000)

0x00

0x5803

RESET_CONFIG

Chip Reset and Configuration

7.5.1

0x01

0x1800

IO_CONFIG

IO Configuration

7.5.2

0x02

0xFFFF

ALM_SD_MASK

Lane Signal Detect Alarm Mask

7.5.3

0x03

0xFFFF

ALM_CLK_MASK

Clock Alarms Mask

7.5.4

0x04

variable(1)

ALM_SD_DET

SERDES Loss of Signal Detection Alarms

7.5.5

0x05

variable(1)

ALM_SYSREF_DET

SYSREF Alignment Circuit Alarms

7.5.6

0x06

variable(1)

TEMP_PLLVOLT

Temperature Sensor and PLL Loop Voltage

7.5.7

0x07-0x08

0x0000

Reserved

0x09

0x0000

PAGE_SET

Page Set

7.5.8

0x0A-0x77

0x0000

Reserved

0x78

0x0000

SYSREF_ALIGN_R

SYSERF Align to r1 and r3 Count

7.5.9

0x79

0x0000

SYSREF12_CNT

SYSREF Phase Count 1 and 2

7.5.10

0x7A

0x0000

SYSREF34_CNT

SYSREF Phase Count 3 and 4

7.5.11

0x7B-0x7E

0x0000

Reserved

0x7F

variable

VENDOR_VER

Vendor ID and Chip Version

7.5.12

Multi-DUC Configuration Registers (PAGE_SET[0] = 1 for multi-DUC1, PAGE_SET[1] = 1 for multi-DUC2)

0x0A

0x02B0

MULTIDUC_CFG1

Multi-DUC Configuration (PAP, Interpolation)

7.5.13

0x0B

0x0000

Reserved

0x0C

0x2402

MULTIDUC_CFG2

Multi-DUC Configuration (Mixers)

7.5.14

0x0D

0x8000

JESD_FIFO

JESD FIFO Control

7.5.15

0x0E

0x00FF

ALM_MASK1

Alarm Mask 1

7.5.16

0x0F

0xFFFF

ALM_MASK2

Alarm Mask 2

7.5.17

0x10

0xFFFF

ALM_MASK3

Alarm Mask 3

7.5.18

0x11

0xFFFF

ALM_MASK4

Alarm Mask 4

7.5.19

0x12

0x0000

JESD_LN_SKEW

JESD Lane Skew

7.5.20

0x13-0x16

0x0000

Reserved

0x17

0x0000

CMIX

CMIX Configuration

7.5.21

0x18

0x0000

Reserved

0x19

0x0000

OUTSUM

Output Summation and Delay

7.5.22

0x1A-0x1B

0x0000

Reserved

0x1C

0x0000

PHASE_NCOAB

Phase offset for AB path NCO

7.5.23

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SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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