DAC38RF80IAAV datasheet(75/160 Pages) TI2

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current for a good phase margin of 69 degrees. If a higher M ratio (for lower PFD frequencies) are required the

charge pump output current must be increased to maintain good loop stability and prevent excessive peaking in

the phase noise response. The charge pump output current setting PLL_CP_ADJ should be adjusted in relation

to the feedback (M) divider ratio PLL_M_M1 according to the following table to maintain a constant phase margin

of 69 degrees.

Table 7-42. M vs Kp for Maintaining Good Stability

CP_ADJ

Similarly for the HF VCO running at 8.847 GHz, and with the M divider set to ÷4, the PFD will run at 552.9375

MHz as shown above. Here the change pump current should set to 6decimal, which gives 600 µA charge pump

output current for a good phase margin of 69 degrees.

7.4.4 CLKOUT

The DAC38RFxx has a programmable output clock on CLKTX+/- balls that is a divided version of the internal

DAC sample clock, either with or without PLL. Two frequency dividers, either DACCLK/3 or DACCLK/4, are

available by programming field CLK_TX_DIV4 in register CLK_OUT (8.5.71). The output swing voltage is

programmable from approximately 125 to 1460 mVPP-DIFF through field CLK_TX_SWING in register CLK_OUT

(8.5.71).

Field CLK_TX_IDLE in register CLK_OUT (8.5.71) enables an idle state, in which the pins are driven to the

proper common-mode levels to charge the external AC coupling caps but the clock output is disabled. The

output clock circuit can be put to sleep by field CLK_TX_SLEEP in register SLEEP_CONFIG (8.5.70).

7.4.5 Serial Peripheral Interface (SPI)

The serial port of the DAC38RFxx is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of DAC38RFxx. It is compatible with most synchronous transfer formats and can be configured

as a 3 or 4 terminal interface by SIF4_ENA in register IO_CONFIG (8.5.2). In both configurations, SCLK is

the serial interface input clock and SDEN is serial interface enable. For 3 terminal configuration, SDIO is a

bidirectional terminal for both data in and data out. For 4 terminal configuration, SDIO is bidirectional and SDO

is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the

falling edge of SCLK.

The SPI registers are reset by writing a 1 to SPI_RESET in register RESET_CONFIG (8.5.1).

Each read/write operation is framed by signal SDEN (Serial Data Enable Bar) asserted low. The first frame byte

is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit

address to be accessed. Figure 7-31 indicates the function of each bit in the instruction cycle and is followed by

a detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 7-31. Instruction Byte of the Serial Interface

Bit

7 (MSB)

Description

R/W

R/W - Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC38RFxx and a low

indicates a write operation to DAC38RFxx

A6:A0 - Identifies the address of the register to be accessed during the read or write operation.

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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