LAN8818D datasheet(63/101 Pages) MICROCHIP

63 / 101 page

LAN8818D

DS00005832C-page 63

Bits in the GPIO Interrupt Status Registers are set by the interrupt events regardless of the value of the corresponding

bits in the GPIO Interrupt Enable Registers.

Each GPIO interrupt polarity can be set individually via the GPIO Interrupt Polarity Registers. When the Interrupt Polarity

bit is set to ‘1’, a high logic level on the GPIO pin will set the corresponding interrupt bit in the GPIO Interrupt Status

Registers. When the Interrupt Polarity bit is set to ‘0’, a low logic level on the GPIO pin will set the corresponding interrupt

bit in the GPIO Interrupt Status Registers.

Any two GPIOs can optionally be used to clear the PTP Timer Interrupt A and PTP Timer Interrupt B, configured using

the PTP GPIO Interrupt Clear Configuration register.

5.18.3

PTP GPIO CAPTURE REGISTERS

Eight GPIOs can be configured to generate PTP GPIO Capture events, stored in eight corresponding PTP GPIO Cap-

ture register sets. GPIOs [15:1] are available for this purpose and are selected via the PTP GPIO Capture Map Regis-

ters.

When a GPIO is configured as an Input and PTP GPIO Capture is enabled via the corresponding bit in the PTP GPIO

Capture Enable register, a rising or falling edge on the GPIO will capture the 1588 LTC value in the corresponding PTP

GPIO Capture register. Rising or falling edge capture behavior is also configured in the PTP GPIO Capture Enable Reg-

isters.

Eight PTP GPIO Capture register sets exist with each set consisting of the following (where “x” is a value between 1

and 8):

• PTP GPIO x Rising Edge LTC Seconds High Capture register

• PTP GPIO x Rising Edge LTC Seconds Low Capture register

• PTP GPIO x Rising Edge LTC Nanoseconds High Capture register

• PTP GPIO x Rising Edge LTC Nanoseconds Low Capture register

• PTP GPIO x Falling Edge LTC Seconds High Capture register

• PTP GPIO x Falling Edge LTC Seconds Low Capture register

• PTP GPIO x Falling Edge LTC Nanoseconds High Capture register

• PTP GPIO x Falling Edge LTC Nanoseconds Low Capture register

Capture status of each PTP GPIO Capture register set is provided in the PTP GPIO Capture Status register and the

corresponding PTP_GPIO interrupt is asserted.

A Lock bit for each GPIO is also provided in the PTP GPIO Capture Lock register, which prevents the corresponding

PTP GPIO Capture Registers from being overwritten (and another interrupt generated) if the corresponding PTP GPIO

Capture Status is already set.

Software can also trigger a Manual PTP Capture into one configurable PTP GPIO Capture register set.

5.18.4

GPIO TIMING

For GPIO timing information, refer to the following Section 6.6, "AC Specifications" sub-sections:

• GPIO Timing

• GPIO SOF Detection Timing

• 1588 GPIO Timing

Note:

Upon reset, GPIOs that were outputs may generate an active interrupt status as the system settles—typi-

cally when a low GPIO pin slowly rises due to the internal pull-up. The interrupt status bits within the GPIO

Interrupt Status Registers must be cleared as part of the device initialization software routine.

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