LAN8818D datasheet(67/101 Pages) MICROCHIP

67 / 101 page

LAN8818D

DS00005832C-page 67

5.20

Power Management

The device incorporates a number of power-management modes and features that provide methods to consume less

energy. These are discussed in the following sections.

5.20.1

SMART POWER SAVING

For shorter cable lengths (< ~70 meters) the SNR is sufficiently high to allow the reduction of ADC resolution as well as

DSP taps. Based on the detected cable length, the device automatically reduces power consumption by approximately

20 mW.

5.20.2

ENERGY-DETECT POWER-DOWN MODE

The device supports an Energy-Detect Power-Down (EDPD) mode to save power when there is no link partner sending

signals.

In EDPD mode, the device shuts down all transceiver blocks, except for the transmitter and energy detect circuits.

Power can be reduced further by extending the time interval between the transmissions of link pulses to check for the

presence of a link partner. The periodic transmission of link pulses is needed to ensure the device and its link partner,

when operating in the same low-power state and with Auto-MDI/MDI-X disabled, can wake up when the cable is con-

nected between them.

By default, EDPD mode is disabled after power-up. EDPD is enabled by setting the p_edpd_en bit in the EDPD Control

EDPD operation may be adjusted via the p_edpd_mask_timer[1:0], p_edpd_timer[1:0], and p_EDPD_random_dis fields

in the EDPD Control register within the MMD address space.

The energy detection change status can be read from the Interrupt Status register. The current energy detection status

can be read from the EDPD low power bit in the Analog Control Register 8.

While the p_edpd_en bit is set, the cable link status will be down, and the energy detection normally monitors pairs A

and B for energy. If the link speed is forced to 1000 Mbps (by disabling auto-negotiation and setting the speed manually),

the energy detection monitors all four pairs. For cable diagnostic purposes, individual wire pairs may be monitored by

forcing the link speed to 1000 Mbps and selecting the wire pair using the EDPD Wire Pair Selection bits in the Analog

Control Register 8.

The device’s PLL is normally enabled during EDPD. It can be set to be disabled during EDPD by setting the DGT_ed-

pd_pll_dis bit in MMD31 Register 19.

Normally, previous register setting are maintained when EDPD mode is cleared. With the PLL disabled, a device reset

occurs following the removal of EDPD (or if the DGT_edpd_pll_dis bit is cleared during EDPD), in which case register

settings will return to their defaults.

5.20.3

SOFTWARE POWER-DOWN MODE

The device supports a Software Power-Down (SPD) mode. This mode is used to power down the device when it is not

in use after power-up. SPD mode is enabled by writing a one to the Power Down bit in the Basic Control register. The

device may also be placed into software power-down by default by setting the MODE_SEL[4:0] configuration straps to

‘0100x’. The device exits the SPD state after a zero is written to the Power Down bit.

Previous register settings are maintained during and following the removal of SPD.

The following remain operational during SPD:

• MII Management Interface

- Only access to the standard registers (0 through 31) is supported.

- Access to MMD address spaces other than MMD Address Space 1 is possible if the spd_clock_gate_override

bit is set.

- Access to MMD Address Space 1 is not possible.

•PLL

- Normally the PLL is enabled during SPD. It may be disabled by setting the spd_pll_disable bit described

below.

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