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SH7124 Datasheet(PDF) 39 Page - Renesas Technology Corp

Part # SH7124
Description  Renesas 32-Bit RISC Microcomputer
PDF  782 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7124 Datasheet(HTML) 39 Page - Renesas Technology Corp

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Section 2
CPU
Rev. 3.00
Sep. 27, 2007
Page 19 of 758
REJ09B0243-0300
2.2.1
General Registers (Rn)
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation. R0 is also used as an index register. With a
number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack
pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the
status register (SR) and program counter (PC) values.
2.2.2
Control Registers
There are three 32-bit control registers, designated status register (SR), global base register
(GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base
address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers.
VBR is used as a base address of the exception handling (including interrupts) vector table.
• Status register (SR)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987654321
0
0000000000000000
RRRRRRRRRRRRRRRR
000000
-
-
111100
-
-
RRRRRR
R/W
R/W
R/W
R/W
R/W
R/W
RR
R/W
R/W
----------------
-
-
-
-
-
-
M
Q
I[3:0]
-
-
S
T
Bit
Bit
name
Default
Read/
Write
Description
31 to 10
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
M
Undefined
R/W
Used by the DIV0U, DIV0S, and DIV1 instructions.
8
Q
Undefined
R/W
Used by the DIV0U, DIV0S, and DIV1 instructions.
7 to 4
I[3:0]
1111
R/W
Interrupt Mask
3, 2
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.



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