SH7124 datasheet(82/782 Pages) RENESAS

82 / 782 page

Section 4

Clock Pulse Generator (CPG)

Rev. 3.00

Sep. 27, 2007

Page 62 of 758

REJ09B0243-0300

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

14 to 12

IFC[2:0]

011

R/W

Internal Clock (I

φ) Frequency Division Ratio

Specify the division ratio of the internal clock (I

φ)

frequency with respect to the output frequency of PLL

circuit. If a prohibited value is specified, subsequent

operation is not guaranteed.

000: Setting prohibited

001:

×1/2

010: Setting prohibited

011:

×1/4 (initial value)

100:

×1/8

Other than above: Setting prohibited

11 to 9

BFC[2:0]

011

R/W

Bus Clock (B

φ) Frequency Division Ratio

Specify the division ratio of the bus clock (B

φ)

frequency with respect to the output frequency of PLL

circuit. If a prohibited value is specified, subsequent

operation is not guaranteed.

000: Setting prohibited

001:

×1/2

010: Setting prohibited

011:

×1/4 (initial value)

100:

×1/8

Other than above: Setting prohibited

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