SH7124 datasheet(85/782 Pages) RENESAS

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Section 4

Clock Pulse Generator (CPG)

Rev. 3.00

Sep. 27, 2007

Page 65 of 758

REJ09B0243-0300

4.5

Changing Frequency

Selecting division ratios for the frequency divider can change the frequencies of the internal clock

φ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). This is controlled by software

through the frequency control register (FRQCR). The following describes how to specify the

frequencies.

1. In the initial state, IFC2 to IFC0 = H'011 (

×1/4), BFC2 to BFC0 = H'011 (×1/4), PFC2 to

PFC0 = H'011 (

×1/4), and MPFC2 to MPFC0 = H'011 (×1/4).

2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM.

3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, and MPFC2 to

MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed at

×8, the

frequencies are determined only be selecting division ratios. When specifying the frequencies,

satisfy the following condition: internal clock (I

φ) ≥ bus clock (Bφ) = peripheral clock (Pφ).

When using the MTU2 clock, specify the frequencies to satisfy the following condition:

internal clock (I

φ) ≥ MTU2 clock (MPφ) ≥ peripheral clock (Pφ).

4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will

change after (1 to 24n) cyc + 11B

φ + 7Pφ.

n: Division ratio specified by the BFC bit in FRQCR (1, 1/2, 1/4, or 1/8)

cyc: Clock obtained by dividing EXTAL by 8 with the PLL.

Note: (1 to 24n) depends on the internal state.

SH7124 Datasheet(PDF) 85 Page - Renesas Technology Corp