SH7124 datasheet(77/782 Pages) RENESAS

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Section 4

Clock Pulse Generator (CPG)

Rev. 3.00

Sep. 27, 2007

Page 57 of 758

REJ09B0243-0300

The clock pulse generator blocks function as follows:

PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or

the EXTAL pin by 8. The multiplication ratio is fixed at

×8.

Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is

connected to the XTAL and EXTAL pins.

Divider: The divider generates clocks with the frequencies to be used by the internal clock (I

φ),

bus clock (B

φ), peripheral clock (Pφ), and MTU2 clock (MPφ).

The frequencies can be selected from 1/2, 1/4 (initial value), and 1/8 times the frequency output

from the PLL circuit. The division ratio should be specified in the frequency control register

(FRQCR).

Oscillation Stop Detection Circuit: This circuit detects an abnormal condition in the crystal

oscillator.

Clock Frequency Control Circuit: The clock frequency control circuit controls the clock

frequency according to the setting in the frequency control register (FRQCR).

Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator

circuit and other modules in sleep or standby mode.

Frequency Control Register (FRQCR): The frequency control register (FRQCR) has control

bits for the frequency division ratios of the internal clock (I

φ), bus clock (Bφ), peripheral clock

φ), and MTU2 clock (MPφ).

Oscillation Stop Detection Control Register (OSCCR): The oscillation stop detection control

through an external pin.

Standby Control Registers 1 to 6 (STBCR1 to STBCR6): The standby control register

(STBCR) has bits for controlling the power-down modes. For details, see section 19, Power-Down

Modes.

SH7124 Datasheet(PDF) 77 Page - Renesas Technology Corp