SH7124 datasheet(80/782 Pages) RENESAS

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Section 4

Clock Pulse Generator (CPG)

Rev. 3.00

Sep. 27, 2007

Page 60 of 758

REJ09B0243-0300

Table 4.4

Frequency Division Ratios Specifiable with FRQCR

FRQCR Division Ratio

Setting

Clock Ratio

Clock Frequency (MHz)*

PLL

Multipli-

cation

Ratio

Input

Clock

×8

1/8

1/4

1/8

1/4

1/2

1/4

1/2

1/8

12.5

1/4

1/8

12.5

1/4

12.5

1/2

1/4

12.5

Notes: *

Clock frequencies when the input clock frequency is assumed to be the shown value.

The internal clock (I

φ) frequency must be 10 to 50 MHz and the peripheral clock (Pφ)

frequency must be 10 to 40 MHz. The bus clock (B

φ) frequency must be equal to the

peripheral clock (P

φ) frequency.

1. The PLL multiplication ratio is fixed at

×8. The division ratio can be selected from ×1/2,

×1/4, and ×1/8 for each clock by the setting in the frequency control register.

2. The output frequency of the PLL circuit is the product of the frequency of the input from

the crystal resonator or EXTAL pin and the multiplication ratio (

×8) of the PLL circuit.

3. The input to the divider is always the output from the PLL circuit.

4. The internal clock (I

φ) frequency is the product of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (

×8) of the PLL circuit, and the

division ratio of the divider. The resultant frequency must be a maximum of 50 MHz

(maximum operating frequency).

5. The peripheral clock (P

φ) frequency is the product of the frequency of the input from the

crystal resonator or EXTAL pin, the multiplication ratio (

×8) of the PLL circuit, and the

division ratio of the divider. The resultant frequency must be a maximum of 40 MHz.

6. When using the MTU2, the MTU2 clock (MP

φ) frequency must be equal to or higher

than the peripheral clock frequency (P

φ). The MTU2 clock (MPφ) frequency are the

product of the frequency of the input from the crystal resonator or EXTAL pin, the

multiplication ratio (

×8) of the PLL circuit, and the division ratio of the divider.

7. The frequency of the CK pin is always be equal to the bus clock (B

φ) frequency.

8. The bus clock (B

φ) frequency must be equal to the peripheral clock (Pφ) frequency.

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