SH7124 datasheet(21/782 Pages) RENESAS

21 / 782 page

Section 1

Overview

Rev. 3.00

Sep. 27, 2007

Page 1 of 758

REJ09B0243-0300

Section 1

Overview

1.1

Features of SH7125 and SH7124

This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates

a Renesas Technology original RISC CPU core with peripheral functions required for system

configuration.

The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one

state (one system clock cycle), which greatly improves instruction execution speed. In addition,

the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become

possible to assemble low-cost, high-performance, and high-functioning systems, even for

applications that were previously impossible with microcomputers, such as real-time control,

which demands high speeds.

In addition, this LSI includes on-chip peripheral functions necessary for system configuration,

such as a ROM, a RAM, timers, a serial communication interface (SCI), an A/D converter, an

interrupt controller (INTC), and I/O ports.

The version of the on-chip ROM is F-ZTAT

TM (Flexible Zero Turn Around Time)* that includes

flash memory. The flash memory can be programmed with a programmer that supports

programming of this LSI, and can also be programmed and erased by software. This enables LSI

chip to be re-programmed at a user-site while mounted on a board.

The features of this LSI are listed in table 1.1.

Note: * F-ZTAT

TM is a trademark of Renesas Technology Corp.

SH7124 Datasheet(PDF) 21 Page - Renesas Technology Corp