SH7124 datasheet(46/782 Pages) RENESAS

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Section 2

CPU

Rev. 3.00

Sep. 27, 2007

Page 26 of 758

REJ09B0243-0300

Table 2.7

Access with Displacement

Type

CPU in this LSI

Example of Other CPUs

16-bit displacement

MOV.W

@(disp,PC),R0

MOV.W

@(R0,R1),R2

........

.DATA.W H'1234

MOV.W

@(H'1234,R1),R2

Note:

Immediate data is referenced by @(disp,PC).

2.4.2

Addressing Modes

Table 2.8 lists addressing modes and effective address calculation methods.

Table 2.8

Addressing Modes and Effective Addresses

Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

direct

Effective address is register Rn.

(Operand is register Rn contents.)



indirect

@Rn

Effective address is register Rn contents.

indirect with

post-increment

@Rn+

Effective address is register Rn contents. A

constant is added to Rn after instruction

execution: 1 for a byte operand, 2 for a word

operand, 4 for a longword operand.

1/2/4

Rn + 1/2/4

After instruction

execution

Byte: Rn + 1

→ Rn

Word: Rn + 2

→ Rn

Longword: Rn + 4

→ Rn

indirect with

pre-decrement

@–Rn

Effective address is register Rn contents,

decremented by a constant beforehand: 1 for a

byte operand, 2 for a word operand, 4 for a

longword operand.

Rn - 1/2/4

1/2/4

Rn - 1/2/4

Byte: Rn – 1

→ Rn

Word: Rn – 2

→ Rn

Longword: Rn – 4

→ Rn

(Instruction

executed with Rn

after calculation)

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