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SH7124 Datasheet(PDF) 79 Page - Renesas Technology Corp |
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SH7124 Datasheet(HTML) 79 Page - Renesas Technology Corp |
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79 / 782 page  Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Sep. 27, 2007 Page 59 of 758 REJ09B0243-0300 4.3 Clock Operating Mode Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Clock Operating Mode Source PLL Circuit Input to Divider EXTAL input or crystal resonator ON ( ×8) ×8 The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10 MHz to 12.5 MHz can be used, the internal clock (I φ) frequency ranges from 10 MHz to 50 MHz. Maximum operating frequencies: I φ = 50 MHz, Bφ = 40 MHz, Pφ = 40 MHz, and MPφ = 40 MHz Table 4.4 shows the frequency division ratios that can be specified with FRQCR. |
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