SH7124 datasheet(119/782 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev. 3.00 Sep. 27, 2007 Page 99 of 758

REJ09B0243-0300

Bit

Bit Name

Initial

Value

R/W

Description

IRQ0F

R/W

Indicates the status of an IRQ0 interrupt request.

• When level detection mode is selected

0: An IRQ0 interrupt has not been detected

[Clearing condition]

Driving pin IRQ0 high

1: An IRQ0 interrupt has been detected

[Setting condition]

Driving pin IRQ0 low

• When edge detection mode is selected

0: An IRQ0 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ0F = 1

 Accepting an IRQ0 interrupt

1: An IRQ0 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ0

Note:

The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when

the level on the pin is low.

6.3.4

Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to

IPRM)

Interrupt priority registers are twelve 16-bit readable/writable registers that set priority levels from

0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and

IPR, refer to table 6.3. Each of the corresponding interrupt priority ranks are established by setting

a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved

bits that are not assigned should be set H'0 (B'0000).

Bit:

Initial value:

R/W:

987654321

0000000000000000

R/W

IPR[15:12]

IPR[11:8]

IPR[7:4]

IPR[3:0]

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