SH7124 datasheet(148/782 Pages) RENESAS

148 / 782 page

Section 7

User Break Controller (UBC)

Rev. 3.00

Sep. 27, 2007

Page 128 of 758

REJ09B0243-0300

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

UBIDA

R/W

User Break Disable A

Enables or disables the user break interrupt request

when the channel A break conditions are satisfied.

0: User break interrupt request is enabled when break

conditions are satisfied

1: User break interrupt request is disabled when break

conditions are satisfied



Reserved

This bit is always read as 0. The write value should

always be 0.

SCMFCA

R/W

L Bus Cycle Condition Match Flag A

When the L bus cycle condition in the break conditions

set for channel A is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The L bus cycle condition for channel A does not

match

1: The L bus cycle condition for channel A matches

SCMFCB

R/W

L Bus Cycle Condition Match Flag B

When the L bus cycle condition in the break conditions

set for channel B is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The L bus cycle condition for channel B does not

match

1: The L bus cycle condition for channel B matches

SCMFDA

R/W

I Bus Cycle Condition Match Flag A

When the I bus cycle condition in the break conditions

set for channel A is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The I bus cycle condition for channel A does not

match

1: The I bus cycle condition for channel A matches

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