SH7124 datasheet(172/782 Pages) RENESAS

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Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 3.00 Sep. 27, 2007 Page 152 of 758

REJ09B0243-0300

Table 9.1

MTU2 Functions

Item

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Count clock

φ/1

φ/4

φ/16

φ/64

TCLKA

TCLKB

TCLKC

TCLKD

φ/1

φ/4

φ/16

φ/64

φ/256

TCLKA

TCLKB

φ/1

φ/4

φ/16

φ/64

φ/1024

TCLKA

TCLKB

TCLKC

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

TCLKA

TCLKB

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

TCLKA

TCLKB

φ/1

φ/4

φ/16

φ/64

General registers

TGRA_0

TGRB_0

TGRE_0

TGRA_1

TGRB_1

TGRA_2

TGRB_2

TGRA_3

TGRB_3

TGRA_4

TGRB_4

TGRU_5

TGRV_5

TGRW_5

General registers/

buffer registers

TGRC_0

TGRD_0

TGRF_0

—

TGRC_3

TGRD_3

TGRC_4

TGRD_4

—

I/O pins

TIOC0A

TIOC0B

TIOC0C

TIOC0D

TIOC1A*

TIOC1B*

TIOC2A*

TIOC2B*

TIOC3A

TIOC3B

TIOC3C

TIOC3D

TIOC4A

TIOC4B

TIOC4C

TIOC4D

Input pins

TIC5U

TIC5V

TIC5W

Counter clear

function

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

0 output

√

—

1 output

√

—

Compare

match

output

Toggle

output

√

—

Input capture

function

√

Synchronous

operation

√

—

PWM mode 1

√

—

PWM mode 2

√

—

Complementary

PWM mode

—

√

—

Reset PWM mode

—

√

—

AC synchronous

motor drive mode

√

—

√

—

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