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TSB12C01A Datasheet(PDF) 32 Page - Texas Instruments |
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TSB12C01A Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 38 page ![]() TSB21LV03 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SLLS230A – MARCH 1996 – REVISED DECEMBER 1996 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION For a Bus Request the length of the LREQ data stream is 7 bits as shown in Table 9. Table 9. LLC Bus Request BIT(S) NAME DESCRIPTION 0 Start Bit Indicates the beginning of the transfer (always 1). 1–3 Request Type Indicates the type of bus request (see Table 12 for the encoding of this field). 4–5 Request Speed Should be 00 for TSB21LV03 100-Mbit/s speed and 01 for 200-Mbit/s speed. 6 Stop Bit Indicates the end of the transfer (always 0). For a Read Register Request the length of the LREQ data stream is 9 bits as shown in Table 10. Table 10. LLC Read Register Access BIT(S) NAME DESCRIPTION 0 Start Bit Indicates the beginning of the transfer (always 1). 1–3 Request Type Always a 100 indicating that this is a read register request. 4–7 Address Identifies the address of the phy register to be read. 8 Stop Bit Indicates the end of the transfer (always 0). For a Write Register Request the Length of the LREQ data stream is 17 bits as shown in Table 11. Table 11. LLC Write Register Access BIT(S) NAME DESCRIPTION 0 Start Bit Indicates the beginning of the transfer (always 1). 1–3 Request Type Always a 101 indicating that this is a write register request. 4–7 Address Identifies the address of the phy register to be written to. 8–15 Data Gives the data that is to be written to the specified register address. 16 Stop Bit Indicates the end of the transfer (always 0). The 3-bit Request Type field has the values shown in Table 12. Table 12. LLC Bus Request Type LREQ1 LREQ2 LREQ3 NAME DESCRIPTION 0 0 0 ImmReq Immediate request. Upon detection of an idle, the LLC takes control of the bus immediately (no arbitration). 0 0 1 IsoReq Isochronous request: the LLC arbitrates for the bus, no gaps. 0 1 0 PriReq Priority request: the LLC arbitrates after a subaction gap, ignores fair protocol. 0 1 1 FairReq Fair request: the LLC arbitrates after a subaction gap, follows fair protocol. 1 0 0 RdReg The LLC returns the specified register contents through a status transfer. 1 0 1 WrReg The LLC writes to the specified register. 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved |
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