TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

33

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

LREQ timing (each cell represents one clock sample time):

LR0

LR1

LR2

LR3

LR(n-2)

LR(n-1)

NOTE A: Each cell represents one clock sample time.

Figure 22. LREQ Timing

For fair or priority access, the LLC requests control of the bus at least one clock after the phy-LLC interface

becomes idle. If the LLC senses that the CTLn terminals are in a receive state (CTL0 = 1, CTL1 = 0), this

indicates that its request has been lost. This is true anytime during or after the LLC sends the bus request

transfer. Additionally, the phy ignores any fair or priority requests if it asserts the receive state while the LLC is

requesting the bus. The LLC then reissues the request one clock after the next interface idle.

The cycle master uses a normal priority request to send a cycle-start message. After receiving a cycle-start

message, the LLC can issue an isochronous bus request. When arbitration is won, the LLC proceeds with the

isochronous transfer of data. The isochronous request register is cleared in the phy once the LLC sends another

type of request or when the isochronous transfer has been completed. The isochronous request must be issued

during a packet reception. Generally this request would be during reception of a cycle-start packet.

The ImmReq request is issued when the LLC needs to send an acknowledgment after reception of a packet

addressed to it. This request must be issued during packet reception. This is done to minimize the delays that

a phy would have to wait between the end of a packet and the transmittal of an acknowledgment. As soon as

the packet ends, the phy immediately grants access of the bus to the LLC. The LLC sends an acknowledgment

to the sender unless the header CRC of the packet turns out to be bad. In this case, the LLC releases the bus

immediately; it is not allowed to send another type of packet on this grant. To guarantee this, the LLC is forced

to wait 160 ns after the end of the packet is received. The phy then gains control of the bus and the

acknowledgement with the CRC error is sent. Then the bus is released and allowed to proceed with another

requests.

Although highly improbable, it is conceivable that two separate nodes can believe that an incoming packet is

intended for them. The nodes then issue a ImmReq request before checking the CRC of the packet. Since both

phys seize control of the bus at the same time, a temporary, localized collision of the bus occurs somewhere

between the competing nodes. This collision would be interpreted by the other nodes on the network as being

a high-impedance line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken node drops

its request and the false line state is removed. The only side effect would be the loss of the intended

acknowledgment packet (this is handled by the higher-layer protocol).

Read/Write Requests

When the LLC requests to read the specified register contents, the phy sends the contents of the register to the

LLC through a status transfer. When an incoming packet is received while the phy is transferring status

information to the LLC, the phy continues to attempt to transfer the contents of the register until it is successful.

For write requests, the phy loads the data field into the appropriately addressed register as soon as the transfer

has been completed. The LLC is allowed to request read or write operations at any time.