TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

34

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Status

A status transfer is initiated by the phy when it has status information to transfer to the LLC. The phy waits until

the interface is idle before starting the transfer. The transfer is initiated by asserting the following on the control

terminals: CTL0 – CTL1 = 01 along with the first two bits of status information on the D0 – D3 terminals. The

phy maintains CTL0 – CTL1 = 01 for the duration of status transfer. The phy may prematurely end a status

transfer by asserting something else other than CTL0 – CTL1 = 01 on the control terminals. This could be caused

by an incoming packet from another node. The phy continues to attempt to complete the transfer until the

information has been successfully transmitted. There must be at least one idle cycle in between consecutive

status transfers.

The phy normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed by

the LLC state machines. The phy sends an entire status packet to the LLC after a request transfer that contains

a read request, or when the phy has pertinent information to send to the LLC or transaction layers. The only

defined condition where the phy automatically sends a register to the LLC is after Self-ID, when it sends the

physical-ID register, which contains the new node address.

The definition of the bits in the status transfer are shown in Table 13 and the timing is shown in Figure 23.

Table 13. 16-Bit Stream Status Request

BIT(S)

NAME

DESCRIPTION

0

Arbitration Reset Gap

Bit 0 indicates that the phy has detected that the bus has been idle for an arbitration reset gap time

(this time is defined in the IEEE 1394–1995 standard). Bit 0 is used by the LLC in its busy/retry

state machine.

1

Subaction Gap

Bit 1 indicates that the phy has detected that the bus has been idle for a subaction gap time (this

time is defined in the IEEE 1394–1995 standard). Bit 1 is used by the LLC to detect the completion

of an isochronous cycle.

2

Bus Reset

Bit 2 indicates that the phy has entered the bus reset state.

3

State Timeout or CPS

Bit 3 indicates that the phy stayed in a particular state for too long a period, which is usually the

effect of a loop in the cable topology, or that the cable power has dropped below the threshold for

reliable operation.

4–7

Address

Bits 4 – 7 hold the address of the phy register whose contents are transferred to the LLC.

8–15

Data

Bits 8 – 15 contain the data that is to be sent to the LLC.

00

01

01

01

00

00

Phy

CTL0, CTL1

00

S[0,1]

00

00

Phy

D0, D1

S[2,3]

S[14,15]

Figure 23. Status Transfer Timing