TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

29

POST OFFICE BOX 655303

APPLICATION INFORMATION

Table 4. Terminals That Need Isolation

TERMINAL

COMMENT

D0 – D7

Isolation circuitry required on data lines used (D0, D1 for S100; D0 – D3 for S200; D0 – D7 for S400)

CTL0, CTL1

Isolation circuitry required

LREQ

Isolation circuitry required

SCLK

Isolation circuitry required

LPS

Isolation circuitry required if implementing link-on packets. When not implementing link-on packets LPS can be tied

high in the phy power domain to always have the phy-LLC interface enabled, but it puts incorrect LLC power status

into Self-ID packet if LLC is powered down.

RESET

RESET only requires isolation circuitry if software control over hardware reset is required. Normally RESET is con-

nected to a 0.1-

µF capacitor in the phy power domain and resets itself upon power up, thus requiring no isolation

circuit. Other means of resetting the phy include:

PD

PD only requires isolation circuitry if software control over the power-down mode is required. When control is not

required PD is normally pulled low in the phy power domain.

CNA

CNA only requires isolation circuitry when cable not active is used in the LLC power domain, for example, to deter-

mine what state to drive the PD terminal. CNA still operates when the phy is in power-down mode and gives LLC

power domain circuitry an indication when a cable has been plugged into the phy and to power up or power down

the phy. Otherwise CNA is not connected and the connected status of a phy port is determined by reading the phy

registers

C/LKON

Isolation circuitry is required if implementing link-on packets. Otherwise C/LKON is not connected to LLC power

domain.

CMC

CMC only requires isolation circuitry if software control over the state of the configuration-manager contender bit is

required. When software control is not required it may be pulled high to be a CMC or low to not be a CMC in the phy

power domain

The bus-holder isolation, as described previously, can be used with mixed voltage systems with modification.

When the driving side is at a low-power-level device then the bus holders on the high-power-level receiving side

pull a high logic level to the higher supply voltage rail. When the transition to the low side takes place, the 3.3-V

swing may not be enough to pass the thresholds if 5-V bus holders are used on the receiving side. To

compensate for this, a 3.3-V bus holder can be used on the inputs to the 5-V device (this requires the 5-V device

to have TTL input thresholds). A diode chain can lower the voltage of the power supplied to the bus holder as

shown in Figure 21. The low-voltage bus holder limits the voltage swing and the thresholds to be compatible

with the swing induced by the low-voltage driver on the other side of the isolation capacitor. When the 5-V device

(an LLC in Figure 21) has TTL inputs, the

≈3.2-V powered bus holder meets those thresholds.