TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

18

POST OFFICE BOX 655303

APPLICATION INFORMATION

Personal Computer

Phy

Video Peripheral

Grounded

AC Input

Phy

RCA Jack Shields

or S-Video Shield

or Tripod

Figure 8. Potential Problem Due To Incorrect Shield Termination

Each node implementing IEEE 1394-1995 must be looked at independently to determine if isolation is required

for that particular application. When it is required the following section should help in determining the best

method of achieving the required isolation. There are three electrical isolation requirements described in Annex

A.4 of the IEEE 1394-1995 standard that should be followed for proper operation and safety of the serial bus.

They deal with isolation of cable shielding, cable-power isolation, and signal-line isolation. The cable shield

isolation is specified in paragraph 4.2.1.4.8 of IEEE 1394-1995 and an example is shown in Figure 3–30 of the

standard. It nominally consists of connecting the outer cable shield to chassis ground through a parallel

combination of a 1-M

Ω resistor and a 0.1-µF capacitor to provide a relatively high-impedance coupling at low

frequencies and a relatively low-impedance coupling at high frequencies. Cable power is described in section

A.4 of IEEE 1394-1995 with explanation and examples. Basically, when a node is going to source cable power,

it must use an isolating supply to provide that power. This supply can be dedicated to supplying cable power

(see Figure 9) or it can be the isolated supply of the entire node (see Figure A–2 of IEEE 1394 draft revision

8.0v2). The remainder of this document addresses signal-line isolation.

IEEE 1394-1995 phy-LLC interface isolation

Annex A in the IEEE 1394-1995 standard discusses the various places that galvanic isolation can be

implemented when necessary to achieve galvanic isolation of the node. One of the most cost effective places

to isolate a node is at the phy-LLC interface due to the relatively small number of signals that need to be isolated.

Annex J of the IEEE 1394-1995 standard illustrates two techniques to achieve phy-LLC galvanic isolation. One

method uses capacitive-isolation circuitry and the other uses a transformer-isolation circuit on each phy-LLC

signal. The capacitive isolation-circuit is able to galvanically isolate up to the working voltage of the capacitors

used in the circuit. The transformer circuit would typically be able to galvanically isolate to higher voltage levels

due to its generally higher voltage capability between primary and secondary windings.

The phy-LLC interface consists of the following signal lines: LLC request (LREQ), system clock (SYSCLK), two

interface control lines (CTL0 and CTL1), and up to 8 data lines (D0 – D7) plus several additional signals that

may or may not require galvanic isolation depending upon the design of the system. These additional signal

lines that may require isolation on Texas Instruments phys are the reset input (RESET), LLC power status (LPS),

power down (PD), configuration manager contender input with link-on output (C/LKON), and cable not active

(CNA).