TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

30

POST OFFICE BOX 655303

APPLICATION INFORMATION

3.3-V Bus

Holder

LLC

Phy

SCLK

SCLK

0.001

µF

5 V

3.3 V

Figure 21. Isolated Mixed-Voltage System

Determination of whether a node requires galvanic isolation of IEEE 1394-1995 nodes is a node-by-node

requirement of the system designer. Isolation of 1394 nodes requires three parts: cable shielding, cable-power

isolation, and signal-line isolation. Cable shielding requires the correct termination of the cable outer shield with

a parallel combination of a 1-M

Ω resistor and a 0.1-µF capacitor. Cable power isolation requires isolation of the

cable power supply when providing power, or keeping cable power physically separate when not providing cable

power, or keeping cable power physically separate when not using cable power exclusively for the entire node

(with no other outside connections). Texas Instruments recommends its bus-holder isolation technique for

signal-line isolation. It is superior in cost and performance to the method described in Annex J of the IEEE

1394-1995 standard. Table 5 compares the aspects of the capacitive isolation shown in the informative Annex

J of IEEE1394-1995 with the TI bus-holder isolation.

Table 5. Implementation Comparison

EXAMPLE COMPARISON FOR 200-Mbits/s NODE (DATA, CTL, LREQ, SYSCLK)

PARAMETERS

ANNEX J METHOD

TI METHOD

TI BUS-HOLDER BENEFITS

External capacitors

14

8

Reduced PWB area

Reduced complexity

Reduced cost

External resistors

48

0

Reduced PWB area

Reduced power

Reduced complexity

Reduced cost

Voltage swing

VDD/2

Rail to rail

Better noise margin

Digital differentiaters on outputs

Required

None

Reduced complexity

Reduced cost

Special threshold requirements

Required

None

Reduced complexity

Reduced cost

Isolation network power drain

Holds input cells at

VDD/2

Method causes no

impact

Minimal quiescent power drain

No special input cell requirement

Reduced cost

Hysteresis on inputs

Requires Schmitt

triggers on inputs

None

Reduced complexity

Reduced cost

Delay through network

Introduces 2-ns to

3-ns delay

Introduces near-zero

delay

Fewer timing issues