TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

31

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

The TSB21LV03 is designed to operate with a LLC such as the TI TSB12LV21, TSB12LV31, and TSB12C01A.

These devices use an interface as described in Annex J of the IEEE 1394-1995 standard. Details of how the

TSB12LV21, TSB12LV31, and TSB12C01A LLC devices operate are described in the LLC data sheets

(i.e.,TSB12LV21, TSB12LV31, and TSB12C01A). The following paragraphs describe the operation of the

phy-LLC interface.

The TSB21LV03 supports 100-/200-Mbit/s data transfer and has four bidirectional data lines, D0 – D3, crossing

the interface. In 100-Mbit/s operation only D0 and D1 terminals are used. In 200 Mbit/s operation, all Dn

terminals are used for data transfer. The unused Dn terminals are driven low. In addition, there are two

bidirectional control lines CTL0 and CTL1, the 50-MHz SYSCLK line from the phy to the LLC, and the LLC

request terminal LREQ from the LLC to the phy. The TSB21LV03 has control of all bidirectional terminals. The

LLC is allowed to drive these terminals only after it has been given permission by the phy. The dedicated LREQ

request terminal is used by the LLC for any activity that it wishes to initiate.

There are four operations that may occur in the phy-LLC interface: request, status, transmit, and receive. With

the exception of the request operation, all actions are initiated by the phy.

When the phy has control of the bus the CTL0 and CTL1 lines are encoded as shown in Table 6.

Table 6. CTLn Status When Phy Has Control of the Bus

CTL0

CTL1

STATUS NAME

DESCRIPTION

0

0

Idle

No activity is occurring (this is the default mode).

0

1

Status

Status information is being sent from the phy to the LLC.

1

0

Receive

An incoming packet is being sent from the phy to the LLC.

1

1

Transmit

The LLC has been given control of the bus to send an outgoing packet.

When the LLC has control of the bus (phy permission) the CTL0 and CTL1 terminals are encoded as shown

in Table 7.

Table 7. CTLn Status When LLC Has Control of the Bus

CTL0

CTL1

STATUS NAME

DESCRIPTION

0

0

Idle

The LLC releases the bus (transmission has been completed).

0

1

Hold

The LLC is holding the bus while data is being prepared for transmission or is sending another packet

without arbitrating.

1

0

Transmit

An outgoing packet is being sent from the LLC to the phy.

1

1

Reserved

None

Request

When the LLC requests the bus or accesses a register that is located in the TSB21LV03, a serial stream of

information is sent across the LREQ line. The length of the stream varies depending on whether the transfer

is a bus request, a read command, or a write command. Regardless of the type of transfer, a start bit of 1 is

required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0 is the most

significant bit, and is transmitted first. The LREQ terminal is required to idle low (logic level 0).

Table 8. LLC Bus-Request or Register-Access-Request Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

7

Read register request

9

Write register request

17