TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

12

POST OFFICE BOX 655303

APPLICATION INFORMATION

internal register configuration

The accessible internal registers of this device are listed in Table 1.

Table 1. Internal Register Configuration

Address

0

1

2

3

4

5

6

7

0000

Physical ID

R

CPS

0001

RHB

IBR

GC

0010

SPD

Rev

NP

0011

AStat1

BStat1

Ch1

Con1

Reserved

0100

AStat2

BStat2

Ch2

Con2

Reserved

0101

AStat3

BStat3

Ch3

Con3

Reserved

0110

LoopInt

CPSInt

CPS

IR

Reserved

C

0111

Reserved

1000

Reserved

Table 2. Internal Register Field Descriptions

FIELD

SIZE

TYPE

DESCRIPTION

AStat(n)

2

Read

only

AStat contains the line state of TPAn. The status is indicated by the following:

11 = high-impedance state

01 = 1

10 = 0

00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output during

transmit and receive operations. The line state outputs are generally valid during arbitration and idle condi-

tions on the bus.

BStat(n)

2

Read

only

BStat contains the line state of TPBn. The status is indicated by the following:

11 = high-impedance state

01 = 1

10 = 0

00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output during

transmit and receive operations. The line state outputs are generally valid during arbitration and idle condi-

tions on the bus.

C

1

R

Bus manager capable. C indicates the state of the Bus Manager Capable input. When set, this bit is used

by the TSB21LV03 to specify in the Self-ID packet that the node is Bus Manager Capable.

Ch(n)

1

Read

only

When Ch = 1, the port is a child, otherwise it is a parent. This bit is invalid after a hardware reset or a bus

reset until tree-ID processing is completed.

Con(n)

1

Read

only

Con indicates the connection status of the port. When Con = 1, the port is connected, otherwise it is dis-

connected. This bit is set to 1 by a hardware reset and is updated to reflect the actual cable connection

status of the port during bus reset. The TSB21LV03 contains connection debounce circuitry that prevents a

new cable connection on a port from initiating a bus reset until the connection status has been stable for at

least 335 ms. A cable disconnect initiates a bus reset immediately. After a hardware reset, the TSB21LV03

sets the connection status of all ports to 0. The TSB21LV03 proceeds with the bus reset, tree-ID, and Self-

ID, but with all ports considered to be disconnected child ports. The TSB21LV03 can not transmit any sig-

nals on the serial bus ports during this time. The TSB21LV03 does report itself as root with a physical ad-

dress of 00h at the completion of Self-ID. If any port is actually connected, after the debounce delay, the

TSB21LV03 initiates another bus reset, which proceeds normally with interaction between the TSB21LV03

and its peer nodes.