TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

35

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Transmit

When the LLC wants to transmit information, it first requests access to the bus through the LREQ terminal. Once

the phy receives this request, it arbitrates to gain control of the bus. When the phy wins ownership of the serial

bus, it grants the bus to the LLC by asserting the transmit state on the CTLn terminals for at least one SYSCLK

cycle, followed by idle for one clock cycle. The LLC takes control of the bus by asserting either hold or transmit

on the CTLn terminals. Hold is used by the LLC to keep control of the bus when it needs some time to prepare

the data for transmission. The phy keeps control of the bus for the LLC by asserting a data-on state on the bus.

It is not necessary for the LLC to use hold when it is ready to transmit as soon as bus ownership is granted.

When the LLC is prepared to send data, it asserts the transmit state on the CTLn terminals as well as sending

the first bits of the packet on the D0 – D3 lines (assuming 200 Mbits/s). The transmit state is held on the CTLn

terminals until the last bits of data have been sent. The LLC then asserts an idle state on the CTLn terminals

for one clock cycle after which it releases control of the interface.

However, there are times when the LLC needs to send another packet without releasing the bus. For example,

the LLC may want to send consecutive isochronous packets or it may want to attach a response to an

acknowledgment. To do this, the LLC asserts a hold state instead of an idle state when the first packet of data

has been completely transmitted. In this case, hold informs the phy that the LLC needs to send another packet

without releasing control of the bus. The phy then waits a set amount of time before asserting a transmit state.

The LLC can then proceed with the transmittal of the second packet. After all data has been transmitted and

the LLC has asserted an idle state on the CTLn terminals, the phy asserts its own idle state on the CTLn

terminals. When sending multiple packets in this fashion, it is required that all data be transmitted at the same

speed. This is required because the transmission speed is set during arbitration and since the arbitration step

is skipped, there is no way of informing the network of a change in speed.

11

00

ZZ

ZZ

ZZ

ZZ

Phy

CTL0, CTL1

ZZ

ZZ

00

ZZ

ZZ

00

0000

0000

ZZZZ

ZZZZ

ZZZZ

ZZZZ

Phy

D0 – D3

ZZZZ

ZZZZ

0000

ZZZZ

ZZZZ

0000

ZZ

ZZ

01

10

10

10

LLC

CTL0, CTL1

00

00

ZZ

01

10

ZZ

ZZZZ

ZZZZ

0000

D0

D1

D2

LLC

D0 – D3

0000

0000

ZZZZ

0000

Dn

ZZZZ

Single Packet

ZZ

ZZ

00

11

00

ZZ

Phy

CTL0, CTL1

ZZ

ZZ

ZZ

00

ZZ

Continued Packet

ZZ

ZZZZ

ZZZZ

0000

0000

0000

ZZZZ

Phy

D0 – D3

ZZZZ

ZZZZ

ZZZZ

0000

ZZZZ

ZZZZ

01

00

ZZ

ZZ

ZZ

01

LLC

CTL0, CTL1

01

10

10

ZZ

10

10

0000

0000

ZZZZ

ZZZZ

ZZZZ

0000

LLC

D0 – D3

0000

D0

D1

ZZZZ

Dn

Dn-1

NOTE A: ZZ = High-impedance state

D0 => Dn = Packet data

Figure 24. Transmit Timing Waveforms