ISL12020M

FN6667 Rev 6.00

Page 32 of 34

January 9, 2015

February 11, 2010

FN6667.4

Updated Note 2 in Ordering Information table from “These Intersil Pb-free plastic packaged products employ

special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.” to “These Intersil plastic packaged products employ special material

sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain

Pb but they are RoHS compliant by exemption 7 (lead in high melt temp solder for internal connections) and

exemption 5 (lead in piezoelectric elements). These Intersil RoHS compliant products are compatible with both

SnPb and Pb-free soldering operations. These Intersil RoHS compliant products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.”

Changed "Pb-Free" in page 1 “Features” and page 4 “Ordering Information” to "RoHS Compliant"

October 22, 2009

Converted to New Intersil Template - Matched front page to match ISL12022M with the exception of pinout

change from SOIC to DFN. Updated ordering information by numbering all notes, setting up links, added MSL

(Moisture Sensitivity Level) note. Updated word "Pinout" to "Pin Configuration". Pin Descriptions updated by

adding descriptive text taken from page 9. Deleted Text Pin Descriptions that were on page 9. Changed Thermal

information from "Tja 85, Tjc 3" To "Tja 40, Tjc 3.5" to match ASYD in Intrepid. Pb-free reflow link now shown in

blue. Updated Notes in Electrical Spec Tables to follow flow of numbers when referenced. Added "boldface

limits..." text in Electrical Spec Conditions to indicate Min and Max over-temp. Bolded all over-temp Min and Max

values. Added Revision History and Products information with links. Updated POD from Rev0 to Rev1 to match

Intrepid. Added Table of Contents.

July 24, 2009

FN6667.3

Page 1: in the Features section, corrected typo in the second bullet from:

20 Ld DFN Package (for SOIC package see ISL12020M)

To:20 Ld DFN Package (for SOIC package see ISL12022M)

No rev, no date change, no formal review necessary

June 22, 2009

Changes in Word document attached in Intrepid.

http://intranet.intrepid.intersil.com/Windchill/servlet/WindchillAuthGW/wt.content.ContentHttp/viewContent

/12020M.doc?u8&HttpOperationItem=wt.content.ApplicationData%3A120896672&ContentHolder=ext.isil.p

art.mcol.MCOL%3A120896665

January 15, 2009

FN6667.2

Added text and equations for Ibat for temp sense ON and for relative accuracy for 1m vs 10m interval

Added text clarifying that no compensation at Vbat<2.7V

Revised entire “DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)” on page 16

Added Application Example for DST - “Daylight Savings Time (DST) Example” on page 29

Added requirement for Vbat>1.8V in Vbat note.

Added apps circuit to survive Vbat<1.8V

Corrected all occurrences of Alpha tables

Bolded and shaded the COMPENSATION registers in Table 1 to indicate they are not to be overwritten. Also

bolded an advisory in the register sections.

Fixed blank bits in register tables and in text.

Register Table 1: Change default values for compensation to xx's, they are different with each device.

Added Datasheet curves

Added statement to Apps section on crystal handling (in “Layout Considerations” on page 28.)

Applied Intersil standards as follows: Updated lead finish note in “Ordering Information”, added Theta JC note

for thermal resistance, updated over-temp note in Electrical Specification tables, numbered equations that were

not initially, updated POD to latest version, which includes following edits:

Note 6 revised from “Soldering required to PCB for X1 and X2 pads each on a separate floating metal (GRN).”to

“The X1 and X2 pads need to be soldered down to the PCB on separate and electrically isolated land pads.”

Minor dimensions included based on customer input and laid out in new format.

On page 6: IDD1 - Changed Max from 6.5 to 7 for VDD = 5V and 5.5 to 6 for VDD = 3V.

On page 3: Remove DeltaATLSB spec

On page 7: Hysteresis spec - Remove Min and set Typ to 0.05 x VDD

on page 8: tHD:DAT - Change Min from 0 to 20

On page 14: For Table 1, yellow shaded and bolded XTO and ALPHAH registers

On page 21: Eq. 3 - Changed "BETAVALUES" to "BETA VALUES"

On page 29: Eq. 7 - Change "ppmerror" to "ppm error"

On page 26: Changed title for Table 28 from “ALPHA REGISTER” to "ALPHA HOT REGISTER"

On Page 16: Under “Initial AT and DT setting Register (ITRO)” on page 18, changed range value from 62.6ppm

to 62.5ppm.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev. (Continued)

DATE

REVISION

CHANGE