ISL12020M

FN6667 Rev 6.00

Page 15 of 34

January 9, 2015

Real Time Clock Registers

Addresses [00h to 06h]

RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)

These registers depict BCD representations of the time. As such,

SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour)

can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31,

MO (Month) is 1 to 12, YR (Year) is 0 to 99 and DW (Day of the

Week) is 0 to 6.

The DW register provides a Day of the Week status and uses three

bits DW2 to DW0 to represent the seven days of the week. The

counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-…

The assignment of a numerical value to a specific day of the

week is arbitrary and may be decided by the system software

designer. The default value is defined as “0”.

24-HOUR TIME

If the MIL bit of the HR register is “1”, the RTC uses a 24-hour

format. If the MIL bit is “0”, the RTC uses a 12-hour format and

HR21 bit functions as an AM/PM indicator with a “1”

representing PM. The clock defaults to 12-hour format time with

HR21 = “0”.

LEAP YEARS

Leap years add the day February 29 and are defined as those years

that are divisible by 4. Years divisible by 100 are not leap years,

unless they are also divisible by 400. This means that the year 2000

is a leap year and the year 2100 is not. The ISL12020M does not

correct for the leap year in the year 2100.

Control and Status Registers

(CSR)

Addresses [07h to 0Fh]

The Control and Status Registers consist of the Status Register,

Interrupt and Alarm Register, Analog Trimming and Digital

Trimming Registers.

Status Register (SR)

The Status Register is located in the memory map at address

07h. This is a volatile register that provides either control or

status of RTC failure (RTCF), Battery Level Monitor (LBAT85,

LBAT75), alarm trigger, Daylight Saving Time, crystal oscillator

enable and temperature conversion in progress bit.

20h

DSTCR

DstMoFd

DSTE

D

D

DstMoFd

20

DstMoFd

13

DstMoFd

12

DstMoFd

11

DstMoFd

10

1 to 12

00h

21h

DstDwFd

D

DstDwFd

E

DstWkFd

12

DstWkFd

11

DstWkFd

10

DstDwFd

12

DstDwFd

11

DstDwFd

10

0 to 6

00h

22h

DstDtFd

D

D

DstDtFd2

1

DstDtFd2

0

DstDtFd1

3

DstDtFd1

2

DstDtFd1

1

DstDtFd1

0

1 to 31

00h

23h

DstHrFd

D

D

DstHrFd2

1

DstHrFd2

0

DstHrFd1

3

DstHrFd1

2

DstHrFd1

1

DstHrFd1

0

0 to 23

00h

24h

DstMoRv

D

D

D

XDstMoR

v20

DstMoRv

13

DstMoR1

2v

DstMoRv

11

DstMoRv

10

01 to 12

00h

25h

DstDwRv

D

DstDwRv

E

DstWkrv1

2

DstWkRv

11

DstWkRv

10

DstDwRv

12

DstDwRv

11

DstDwRv

10

0 to 6

00h

26h

DstDtRv

D

D

DstDtRv2

1

DstDtRv2

0

DstDtRv1

3

DstDtRv1

2

DstDtRv1

1

DstDtRv1

0

01 to 31

00h

27h

DstHrRv

D

D

DstHrRv2

1

DstHrRv2

0

DstHrRv1

3

DstHrRv1

2

DstHrRv1

1

DstHrRv1

0

0 to 23

00h

28h

TEMP

TK0L

TK07

TK06

TK05

TK04

TK03

TK02

TK01

TK00

00 to FF

00h

29h

TK0M

000000

TK09

TK08

00 to 03

00h

2Ah

NPPM

NPPML

NPPM7

NPPM6

NPPM5

NPPM4

NPPM3

NPPM2

NPPM1

NPPM0

00 to FF

00h

2Bh

NPPMH

00000

NPPM10

NPPM9

NPPM8

00 to 07

00h

2Ch

XT0

XT0

D

D

D

XT4

XT3

XT2

XT1

XT0

00 to FF

XXh

2Dh

ALPHAH

ALPHAH

D

ALP_H6

ALP_H5

ALP_H4

ALP_H3

ALP_H2

ALP_H1

ALP_H0

00 to 7F

XXh

2Eh

GPM

GPM1

GPM17

GPM16

GPM15

GPM14

GPM13

GPM12

GPM11

GPM10

00 to FF

00h

2Fh

GPM2

GPM27

GPM26

GPM25

GPM24

GPM23

GPM22

GPM21

GPM20

00 to FF

00h

TABLE 1. REGISTER MEMORY MAP (X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW SHADING INDICATES THOSE BITS SHOULD NOT BE

CHANGED BY THE USER) (Continued)

ADDR. SECTION

REG

NAME

BIT

RANGE

DEFAULT

7

654321

0