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FN6667 Datasheet(PDF) 28 Page - Renesas Technology Corp |
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FN6667 Datasheet(HTML) 28 Page - Renesas Technology Corp |
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28 / 34 page ![]() ISL12020M FN6667 Rev 6.00 Page 28 of 34 January 9, 2015 Application Section Power Supply Considerations The ISL12022M contains programmed EEPROM registers which are recalled to volatile RAM registers during initial power-up. These registers contain DC voltage, frequency and temperature calibration settings. Initial power-up can be either application of VBAT or VDD power, whichever is first. It is important that the initial power-up meet the power supply slew rate specification to avoid faulty EEPROM power-up recall. Also, any glitches or low voltage DC pauses should be avoided, as these may activate recall at a low voltage and load erroneous data into the calibration registers. Note that a very slow VDD ramp rate (outside data sheet limits) will almost always trigger erroneous recall and should be avoided entirely. Battery-Backup Details The ISL12020M has automatic switchover to battery-backup when the VDD drops below the VBAT mode threshold. A wide variety of backup sources can be used, including standard and rechargeable lithium, Super Capacitors, or regulated secondary sources. The serial interface is disabled in battery-backup, while the oscillator and RTC registers are operational. The SRAM register contents are powered to preserve their contents as well. The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind the temperature compensation only operates for VBAT > 2.7V. Note that the device is not guaranteed to operate with a VBAT < 1.8V, so the battery should be changed before discharging to that level. It is strongly advised to monitor the low battery indicators in the status registers and take action to replace discharged batteries. If a Super Capacitor is used, it is possible that it may discharge to below 1.8V during prolonged power-down. Once powered up, the device may lose serial bus communications until both VDD and VBAT are powered down together. To avoid that situation, including situations where a battery may discharge deeply, the circuit in Figure 21 can be used. The diode, DBAT, will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8V. The jumper is added as a safeguard should the battery ever need to be disconnect from the circuit. . The VDD negative slew rate should be limited to below the data sheet spec (10V/ms) otherwise battery switchover can be delayed, resulting in SRAM contents corruption and oscillator operation interruption. Some applications will require separate supplies for the RTC VDD and the I2C pullups. This is not advised, as it may compromise the operation of the I2C bus. For applications that do require serial bus communication with the RTC VDD powered down, the SDA pin must be pulled low during the time the RTC VDD ramps down to 0V. Otherwise, the device may lose serial bus communications once VDD is powered up and will return to normal operation ONLY once VDD and VBAT are both powered down together. Layout Considerations The ISL12020M contains a quarts crystal and requires special handling during PC board assembly. Excessive shock and vibrations should be avoided. Ultrasound cleaning is not advisable. See Note 7 on page 6 in the electrical specifications table pertaining to solder reflow effects on oscillator accuracy. The crystal pins X1 and X2 have a very high impedance and oscillator circuits operating at low frequencies (such as 32.768kHz) are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking. FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN) SIGNALS FROM THE MASTER SIGNALS FROM THE SLAVE SIGNAL AT SDA S T A R T IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE A C K A C K 0 S T O P A C K 1 IDENTIFICATION BYTE WITH R/W = 1 A C K S T A R T LAST READ DATA BYTE FIRST READ DATA BYTE A C K 10 1 1111 10 1 11 11 FIGURE 21. SUGGESTED BATTERY-BACKUP CIRCUIT DBAT CBAT CIN BAT43W 0.1µF 0.1µF VDD = 2.7V TO 5.5V VBAT = 1.8V TO 3.2V JBAT ISL12020M VDD GND VBAT + |
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