ISL12020M

FN6667 Rev 6.00

Page 7 of 34

January 9, 2015

FoutT

Oscillator Stability vs Temperature

VDD = 3.3V, 0°C to +85°C

-5

+5

ppm

7, 15

VDD = 3.3V, -30°C to +85°C

-10

+10

ppm

7, 15

VDD = 3.3V, -40°C to +85°C

-15

+15

ppm

7, 15

FoutV

Oscillator Stability vs Voltage

2.7V

 VDD  5.5V

-3

+3

ppm

15

Temperature Sensor Accuracy

VDD = VBAT = 3.3V

±2

°C

15

IRQ/FOUT (OPEN-DRAIN OUTPUT)

VOL

Output Low Voltage

VDD = 5V, IOL = 3mA

0.4

V

VDD = 2.7V, IOL = 1mA

0.4

V

DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA= -40°C to +85°C, unless otherwise stated. Boldface

limits apply across the operating temperature range, -40°C to +85°C. (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

(Note 8)

TYP

(Note 9)

MAX

(Note 8)

UNITS

NOTES

Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply

across the operating temperature range, -40°C to +85°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

(Note 8)

TYP

(Note 9)

MAX

(Note 8)

UNITS

NOTES

VDDSR-

VDD Negative Slew Rate

10

V/ms

14

VDDSR+

VDD Positive Slew Rate, Minimum

.05

V/ms

17

I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

Boldface limits apply across the operating temperature range, -40°C to +85°C.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 8)

TYP

(Note 9)

MAX

(Note 8)

UNITS

NOTES

VIL

SDA and SCL Input Buffer LOW

Voltage

-0.3

0.3 x VDD

V

VIH

SDA and SCL Input Buffer HIGH

Voltage

0.7 x VDD

VDD + 0.3

V

Hysteresis

SDA and SCL Input Buffer

Hysteresis

0.05 x VDD

V

15, 16

VOL

SDA Output Buffer LOW Voltage,

Sinking 3mA

VDD = 5V, IOL = 3mA

0

0.02

0.4

V

CPIN

SDA and SCL Pin Capacitance

TA = +25°C, f = 1MHz,

VDD = 5V, VIN =0V,

VOUT = 0V

10

pF

15, 16

fSCL

SCL Frequency

400

kHz

tIN

Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the

max spec is suppressed.

50

ns

tAA

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing

30% of VDD, until SDA exits

the 30% to 70% of VDD

window.

900

ns

tBUF

Time the Bus Must be Free Before

the Start of a New Transmission

SDA crossing 70% of VDD

during a STOP condition, to

SDA crossing 70% of VDD

during the following START

condition.

1300

ns

tLOW

Clock LOW Time

Measured at the 30% of VDD

crossing.

1300

ns