FN6667 datasheet(22/34 Pages) RENESAS

22 / 34 page

ISL12020M

FN6667 Rev 6.00

Page 22 of 34

January 9, 2015

Final Analog Trimming Register (FATR)

This register shows the final setting of AT after temperature

correction. It is read-only; the user cannot overwrite a value to this

temperature compensation function. See Tables 18 and 19 (for

values).

Final Digital Trimming Register (FDTR)

This register shows the final setting of DT after temperature

correction. It is read-only; the user cannot overwrite a value to

this register. The value is accessible as a means of monitoring

the temperature compensation function. The corresponding

clock adjustment values are shown in Table 20. The FDTR setting

has both positive and negative settings to adjust for any offset in

the crystal..

ALARM Registers (10h to 15h)

The alarm register bytes are set up identical to the RTC register

bytes, except that the MSB of each byte functions as an enable

bit (enable = “1”). These enable bits specify which alarm

registers (seconds, minutes, etc.) are used to make the

comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the alarm

registers and the RTC registers. As the RTC advances, the alarm

will be triggered once a match occurs between the alarm

registers and the RTC registers. Any one alarm register, multiple

registers, or all registers can be enabled for a match.

There are two alarm operation modes: Single Event and periodic

Interrupt Mode:

• Single Event Mode is enabled by setting the bit 7 on any of the

Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0” and

disabling the frequency output. This mode permits a one-time

match between the Alarm registers and the RTC registers.

Once this match occurs, the ALM bit is set to “1” and the

IRQ/FOUT output will be pulled low and will remain low until

the ALM bit is reset. This can be done manually or by using the

auto-reset feature.

• Interrupt Mode is enabled by setting the bit 7 on any of the

Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1” and

disabling the frequency output. The IRQ/FOUT output will now

be pulsed each time an alarm occurs. This means that once

the interrupt mode alarm is set, it will continue to alarm for

each occurring match of the alarm and present time. This

mode is convenient for hourly or daily hardware interrupts in

microcontroller applications such as security cameras or utility

meter reading.

To clear a single event alarm, the ALM bit in the status register

must be set to “0” with a write. Note that if the ARST bit is set to

1 (address 08h, bit 7), the ALM bit will automatically be cleared

when the status register is read.

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1

• Alarm set with single interrupt (IM = “0”)

• A single alarm will occur on January 1 at 11:30 a.m.

• Set Alarm registers as follows:

TABLE 18. FINAL ANALOG TRIMMING REGISTER

ADDR

0Eh

FATR5

FATR4 FATR3 FATR2 FATR1 FATR0

TABLE 19. FINAL DIGITAL TRIMMING REGISTER

ADDR

765

0Fh

FDTR4 FDTR3 FDTR2

FDTR1

FDTR0

TABLE 20. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL

TRIMMING REGISTER

FDTR<4:0>

DECIMAL

ppm ADJUSTMENT

00000

00001

30.5

00010

00011

91.5

00100

122

00101

152.5

00110

183

00111

213.5

01000

244

01001

274.5

01010

305

10000

10001

-1

-30.5

10010

-2

-61

10011

-3

-91.5

10100

-4

-122

10101

-5

-152.5

10110

-6

-183

10111

-7

-213.5

11000

-8

-244

11001

-9

-274.5

11010

-10

-305

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