FN6667 datasheet(23/34 Pages) RENESAS

23 / 34 page

ISL12020M

FN6667 Rev 6.00

Page 23 of 34

January 9, 2015

After these registers are set, an alarm will be generated when the

RTC advances to exactly 11:30 a.m. on January 1 (after seconds

changes from 59 to 00) by setting the ALM bit in the status register

to “1” and also bringing the IRQ/FOUT output low.

Example 2

• Pulsed interrupt once per minute (IM = “1”)

• Interrupts at one minute intervals when the seconds register is

at 30s.

• Set Alarm registers as follows:

Once the registers are set, the following waveform will be seen at

IRQ/FOUT:

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

Time Stamp VDD to Battery Registers (TSV2B)

The TSV2B Register bytes are identical to the RTC register bytes,

except they do not extend beyond the Month. The Time Stamp

captures the FIRST VDD to Battery Voltage transition time and will

not update upon subsequent events, until cleared (only the first

event is captured before clearing). Set CLRTS = 1 to clear this

Note that the time stamp registers are cleared to all “0”,

including the month and day, which is different from the RTC and

alarm registers (those registers default to 01h). This is the

indicator that no time stamping has occurred since the last clear

or initial power-up. Once a time stamp occurs, there will be a

non-zero time stamp.

Time Stamp Battery to VDD Registers (TSB2V)

The Time Stamp Battery to VDD Register bytes are identical to

the RTC register bytes, except they do not extend beyond Month.

The Time Stamp captures the LAST transition of VBAT to VDD

(only the last event of a series of power-up/down events is

retained). Set CLRTS = 1 to clear this register (Add 09h,

PWR_VDD register).

DST Control Registers (DSTCR)

8 bytes of control registers have been assigned for the Daylight

Savings Time (DST) functions. DST beginning (set Forward) time

is controlled by the registers DstMoFd, DstDwFd, DstDtFd and

DstHrFd. DST ending time (set Backward or Reverse) is controlled

by DstMoRv, DstDwRv, DstDtRv and DstHrRv.

Tables 23 and 24 describe the structure and functions of the DSTCR.

DST FORWARD REGISTERS (20H TO 23H)

DST forward is controlled by the following DST Registers:

DST Enable

DSTE is the DST Enabling Bit located in Bit 7 of register 20h

(DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon

powering up for the first time (including battery), the DSTE bit

defaults to “0”. When DSTE is set to “1” the RTC time must be at

least one hour before the scheduled DST time change for the

correction to take place. When DSTE is set to “0”, the DSTADJ bit

in the Status Register automatically resets to “0”.

DST Month Forward

DstMoFd sets the Month that DST starts. The format is the same

as for the RTC register month, from 1 to 12. The default value for

the DST begin month is 00h.

DST Day/Week Forward

DstDwFd contains both the Day of the Week and the Week of the

Month data for DST Forward control. DST can be controlled either

by actual date or by setting both the Week of the month and the

Day of the Week. DstDwFdE sets the priority of the Day/Week

over the Date. For DstDwFdE = 1, Day/Week is the priority. You

must have the correct Day of Week entered in the RTC registers

for the Day/Week correction to work properly.

TABLE 21.

ALARM

BIT

DESCRIPTION

76543210

HEX

SCA0

00000000

00h Seconds disabled

MNA0

10110000

B0h Minutes set to 30,

enabled

HRA0

10010001

91h Hours set to 11,

enabled

DTA0

10000001

81h Date set to 1,

enabled

MOA0

10000001

81h Month set to 1,

enabled

DWA0

00000000

00h Day of week

disabled

TABLE 22.

ALARM

BIT

DESCRIPTION

76543210 HEX

SCA0

10110000 B0h Seconds set to 30,

enabled

MNA0

00000000 00h Minutes disabled

HRA0

00000000 00h Hours disabled

DTA0

00000000 00h Date disabled

MOA0

00000000 00h Month disabled

DWA0

00000000 00h Day of week disabled

60s

RTC AND ALARM REGISTERS ARE BOTH “30s”

FIGURE 15. IRQ/FOUT WAVEFORM

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