ISL12020M

FN6667 Rev 6.00

Page 8 of 34

January 9, 2015

tHIGH

Clock HIGH Time

Measured at the 70% of VDD

crossing.

600

ns

tSU:STA

START Condition Setup Time

SCL rising edge to SDA

falling edge. Both crossing

70% of VDD.

600

ns

tHD:STA

START Condition Hold Time

From SDA falling edge

crossing 30% of VDD to SCL

falling edge crossing 70% of

VDD.

600

ns

tSU:DAT

Input Data Setup Time

From SDA exiting the 30% to

70% of VDD window, to SCL

rising edge crossing 30% of

VDD.

100

ns

tHD:DAT

Input Data Hold Time

From SCL falling edge

crossing 30% of VDD to SDA

entering the 30% to 70% of

VDD window.

20

900

ns

tSU:STO

STOP Condition Setup Time

From SCL rising edge

crossing 70% of VDD, to SDA

rising edge crossing 30% of

VDD.

600

ns

tHD:STO

STOP Condition Hold Time

From SDA rising edge to SCL

falling edge. Both crossing

70% of VDD.

600

ns

tDH

Output Data Hold Time

From SCL falling edge

crossing 30% of VDD, until

SDA enters the 30% to 70%

of VDD window.

0

ns

tR

SDA and SCL Rise Time

From 30% to 70% of VDD.

20 + 0.1 x

Cb

300

ns

16

tF

SDA and SCL Fall Time

From 70% to 30% of VDD.

20 + 0.1 x

Cb

300

ns

16

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip

10

400

pF

16

RPU

SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by

tR and tF.

For Cb = 400pF, max is

about 2kΩ~2.5kΩ.

For Cb = 40pF, max is about

15kΩ~20kΩ

1

kΩ

16

NOTES:

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

9. Specified at +25°C.

10. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested.

11. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT<1.8V.

12. IRQ/FOUT Inactive.

13. VDD > VBAT +VBATHYS

14. In order to ensure proper timekeeping, the VDD SR- specification must be followed.

15. Limits should be considered typical and are not production tested.

16. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate

specification.

17. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.

I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.

Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 8)

TYP

(Note 9)

MAX

(Note 8)

UNITS

NOTES